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machxo2: Add prefix parameter to simple.sh. Update README.md.

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William D. Jones 2021-02-08 16:55:26 -05:00 committed by gatecat
parent 0b0faa2f1c
commit 730e543ca6
2 changed files with 14 additions and 14 deletions
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8
machxo2/examples/README.md
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@ -1,8 +1,8 @@
# MachXO2 Architecture Example # MachXO2 Architecture Example
This directory contains a simple example of running `nextpnr-machxo2`: This directory contains a simple example of running `nextpnr-machxo2`:
* `simple.sh` generates JSON output (`{pack,place,pnr}blinky.json`) of a * `simple.sh` produces nextpnr output in the files `{pack,place,pnr}*.json`,
classic blinky example from `blinky.v`. as well as pre-pnr and post-pnr diagrams in `{pack,place,pnr}*.{dot, png}`.
* `simtest.sh` will use `yosys` to generate a Verilog file from * `simtest.sh` will use `yosys` to generate a Verilog file from
`{pack,place,pnr}blinky.json`, called `{pack,place,pnr}blinky.v`. It will `{pack,place,pnr}blinky.json`, called `{pack,place,pnr}blinky.v`. It will
then and compare `{pack,place,pnr}blinky.v`'s simulation behavior to the then and compare `{pack,place,pnr}blinky.v`'s simulation behavior to the
@ -10,8 +10,8 @@ This directory contains a simple example of running `nextpnr-machxo2`:
compiler and `vvp` runtime. This is known as post-place-and-route simulation. compiler and `vvp` runtime. This is known as post-place-and-route simulation.
* `mitertest.sh` is similar to `simtest.sh`, but more comprehensive. This * `mitertest.sh` is similar to `simtest.sh`, but more comprehensive. This
script creates a [miter circuit](https://www21.in.tum.de/~lammich/2015_SS_Seminar_SAT/resources/Equivalence_Checking_11_30_08.pdf) script creates a [miter circuit](https://www21.in.tum.de/~lammich/2015_SS_Seminar_SAT/resources/Equivalence_Checking_11_30_08.pdf)
to compare the output port values of `{pack,place,pnr}blinky.v` against the to compare the output port values of `{pack,place,pnr}*.v` against the
original `blinky.v` _when both modules are fed the same values on their input original Verilog code _when both modules are fed the same values on their input
ports._ ports._
All possible inputs and resulting outputs can be tested in reasonable time by All possible inputs and resulting outputs can be tested in reasonable time by

20
machxo2/examples/simple.sh
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@ -1,11 +1,11 @@
#!/usr/bin/env bash #!/usr/bin/env bash
if [ $# -lt 1 ]; then if [ $# -lt 2 ]; then
echo "Usage: $0 mode" echo "Usage: $0 prefix mode"
exit -1 exit -1
fi fi
case $1 in case $2 in
"pack") "pack")
NEXTPNR_MODE="--pack-only" NEXTPNR_MODE="--pack-only"
;; ;;
@ -23,12 +23,12 @@ esac
set -ex set -ex
${YOSYS:-yosys} -p "read_verilog blinky.v ${YOSYS:-yosys} -p "read_verilog ${1}.v
synth_machxo2 -json blinky.json synth_machxo2 -json ${1}.json
show -format png -prefix blinky" show -format png -prefix ${1}"
${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
read_json ${1}blinky.json read_json ${2}${1}.json
clean -purge clean -purge
show -format png -prefix ${1}blinky show -format png -prefix ${2}${1}
write_verilog -noattr -norename ${1}blinky.v" write_verilog -noattr -norename ${2}${1}.v"