ecp5: Simple packer working
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah
parent
f138368e34
commit
74cbaa5b83
@ -177,7 +177,7 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
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void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
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{
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lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = str_or_default(lc->params, ctx->id("INIT"), "0");
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lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = str_or_default(lut->params, ctx->id("INIT"), "0");
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replace_port(lut, ctx->id("A"), lc, ctx->id("A" + std::to_string(index)));
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replace_port(lut, ctx->id("B"), lc, ctx->id("B" + std::to_string(index)));
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replace_port(lut, ctx->id("C"), lc, ctx->id("C" + std::to_string(index)));
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36
ecp5/pack.cc
36
ecp5/pack.cc
@ -71,6 +71,15 @@ class Ecp5Packer
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}
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}
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const NetInfo *net_or_nullptr(CellInfo *cell, IdString port)
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{
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auto fnd = cell->ports.find(port);
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if (fnd == cell->ports.end())
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return nullptr;
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else
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return fnd->second.net;
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}
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// Return whether two FFs can be packed together in the same slice
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bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
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{
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@ -88,11 +97,11 @@ class Ecp5Packer
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if (str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK") !=
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str_or_default(ff1->params, ctx->id("CLKMUX"), "CLK"))
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return false;
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if (ff0->ports.at(ctx->id("CLK")).net != ff1->ports.at(ctx->id("CLK")).net)
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if (net_or_nullptr(ff0, ctx->id("CLK")) != net_or_nullptr(ff1, ctx->id("CLK")))
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return false;
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if (ff0->ports.at(ctx->id("CE")).net != ff1->ports.at(ctx->id("CE")).net)
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if (net_or_nullptr(ff0, ctx->id("CE")) != net_or_nullptr(ff1, ctx->id("CE")))
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return false;
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if (ff0->ports.at(ctx->id("LSR")).net != ff1->ports.at(ctx->id("LSR")).net)
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if (net_or_nullptr(ff0, ctx->id("LSR")) != net_or_nullptr(ff1, ctx->id("LSR")))
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return false;
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return true;
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}
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@ -275,6 +284,8 @@ class Ecp5Packer
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ff_to_slice(ctx, ff, packed.get(), 0, true);
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packed_cells.insert(ff->name);
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sliceUsage[packed->name].ff0_used = true;
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lutffPairs.erase(ci->name);
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fflutPairs.erase(ff->name);
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}
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new_cells.push_back(std::move(packed));
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@ -304,10 +315,14 @@ class Ecp5Packer
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if (ff0 != lutffPairs.end()) {
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ff_to_slice(ctx, ctx->cells.at(ff0->second).get(), slice.get(), 0, true);
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packed_cells.insert(ff0->second);
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lutffPairs.erase(lut0->name);
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fflutPairs.erase(ff0->second);
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}
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if (ff1 != lutffPairs.end()) {
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ff_to_slice(ctx, ctx->cells.at(ff1->second).get(), slice.get(), 1, true);
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packed_cells.insert(ff1->second);
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lutffPairs.erase(lut1->name);
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fflutPairs.erase(ff1->second);
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}
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new_cells.push_back(std::move(slice));
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@ -333,6 +348,8 @@ class Ecp5Packer
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if (ff != lutffPairs.end()) {
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ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 0, true);
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packed_cells.insert(ff->second);
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lutffPairs.erase(ci->name);
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fflutPairs.erase(ff->second);
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}
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new_cells.push_back(std::move(slice));
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@ -374,14 +391,7 @@ class Ecp5Packer
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new_init |= (1 << i);
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}
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}
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cell->params[ctx->id("INIT")] = std::to_string(init);
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NetInfo *innet = cell->ports.at(input).net;
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if (innet != nullptr) {
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innet->users.erase(
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std::remove_if(innet->users.begin(), innet->users.end(),
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[cell, input](PortRef port) { return port.cell == cell && port.port == input; }),
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innet->users.end());
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}
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cell->params[ctx->id("INIT")] = std::to_string(new_init);
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cell->ports.at(input).net = nullptr;
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}
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@ -418,7 +428,7 @@ class Ecp5Packer
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log_info("Packing constants..\n");
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std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
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gnd_cell->params[ctx->id("LUT_INIT")] = "0";
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gnd_cell->params[ctx->id("INIT")] = "0";
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std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
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gnd_net->name = ctx->id("$PACKER_GND_NET");
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gnd_net->driver.cell = gnd_cell.get();
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@ -426,7 +436,7 @@ class Ecp5Packer
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gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
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std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
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vcc_cell->params[ctx->id("LUT_INIT")] = "65535";
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vcc_cell->params[ctx->id("INIT")] = "65535";
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std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
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vcc_net->name = ctx->id("$PACKER_VCC_NET");
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vcc_net->driver.cell = vcc_cell.get();
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@ -1,4 +1,4 @@
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module top(input clk_pin, input btn_pin, output [3:0] led_pin, output gpio0_pin);
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module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin);
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wire clk;
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wire [7:0] led;
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@ -72,6 +72,6 @@ module top(input clk_pin, input btn_pin, output [3:0] led_pin, output gpio0_pin)
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assign led = led_reg;
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// Tie GPIO0, keep board from rebooting
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TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
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assign gpio0 = 1'b1;
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endmodule
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52
ecp5/synth/counter.v
Normal file
52
ecp5/synth/counter.v
Normal file
@ -0,0 +1,52 @@
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module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin);
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wire clk;
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wire [7:0] led;
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wire btn;
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wire gpio0;
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(* BEL="X0/Y35/PIOA" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk));
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(* BEL="X4/Y71/PIOA" *) (* IO_TYPE="LVCMOS33" *) (* keep *)
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TRELLIS_IO #(.DIR("INPUT")) btn_buf (.B(btn_pin), .O(btn));
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(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin[0]), .I(led[0]));
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(* BEL="X0/Y23/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(led_pin[1]), .I(led[1]));
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(* BEL="X0/Y26/PIOA" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(led_pin[2]), .I(led[2]));
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(* BEL="X0/Y26/PIOC" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3]));
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(* BEL="X0/Y26/PIOB" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4]));
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(* BEL="X0/Y32/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5]));
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(* BEL="X0/Y26/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6]));
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(* BEL="X0/Y29/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7]));
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(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
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localparam ctr_width = 30;
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localparam ctr_max = 2**ctr_width - 1;
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reg [ctr_width-1:0] ctr = 0;
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reg [9:0] pwm_ctr = 0;
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reg dir = 0;
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always@(posedge clk) begin
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ctr <= ctr + 1'b1;
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end
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assign led = ctr[ctr_width-1:ctr_width-8];
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// Tie GPIO0, keep board from rebooting
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assign gpio0 = 1'b1;
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endmodule
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