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xilinx: Few more stub timings

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2024-09-26 17:30:36 +02:00
parent 118ecbc6b3
commit 7516b8950a
1 changed files with 18 additions and 0 deletions
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18
himbaechel/uarch/xilinx/gen/xilinx_gen.py
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@ -4,6 +4,7 @@ import argparse
import xilinx_device
import filters
import struct
import parse_sdf
sys.path.append(path.join(path.dirname(__file__), "../../.."))
from himbaechel_dbgen.chip import *
@ -251,6 +252,15 @@ def import_tiletype(ch: Chip, tile: xilinx_device.Tile):
if pip.is_bidi():
add_pip(pip.dst_wire().name(), pip.src_wire().name(), pip_class=PipClass.TILE_ROUTING, timing=tcls,
pip_config=1 if pip.is_route_thru() else 0)
def import_sdf_timings(variant, sdfcell):
# TODO: anything other than comb
for entry in sdfcell.entries:
if isinstance(entry, parse_sdf.IOPath):
variant.add_comb_arc(entry.from_pin, entry.to_pin,
TimingValue(int(min(entry.rising.minv, entry.falling.minv)*1000),
int(max(entry.rising.maxv, entry.falling.maxv)*1000)))
def main():
xlbase = path.join(path.dirname(path.realpath(__file__)), "..")
@ -355,6 +365,14 @@ def main():
ff.add_setup_hold("CK", "SR", ClockEdge.RISING, TimingValue(100, 100), TimingValue(0, 0))
ff.add_setup_hold("CK", "D", ClockEdge.RISING, TimingValue(100, 100), TimingValue(200, 200))
ff.add_clock_out("CK", "Q", ClockEdge.RISING, TimingValue(300, 350))
# Load SDF for carry and mux
slicem_sdf = parse_sdf.parse_sdf_file(path.join(xraydb_root, "timings", "slicem.sdf"))
mux = ch.timing.add_cell_variant("DEFAULT", "SELMUX2_1")
import_sdf_timings(mux, slicem_sdf.cells[("SELMUX2_1", "SLICEM/F7BMUX")])
carry = ch.timing.add_cell_variant("DEFAULT", "CARRY4")
import_sdf_timings(carry, slicem_sdf.cells[("CARRY4", "SLICEM")])
# Import package pins
for package_name, package in sorted(d.packages.items(), key=lambda x:x[0]):
pkg = ch.create_package(package_name)