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Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fix

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interchange: Enable Werror on CI and fix some compile warnings
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gatecat 2021-09-30 11:05:32 +01:00 committed by GitHub
commit 7550b60069
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3 changed files with 10 additions and 7 deletions
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2
.github/ci/build_interchange.sh vendored
View File

@ -57,7 +57,7 @@ function build_nextpnr {
build_capnp
mkdir build
pushd build
cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} -DPYTHON_INTERCHANGE_PATH=${PYTHON_INTERCHANGE_PATH}
cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} -DPYTHON_INTERCHANGE_PATH=${PYTHON_INTERCHANGE_PATH} -DWERROR=on
make nextpnr-fpga_interchange -j`nproc`
popd
}

12
fpga_interchange/arch_pack_clusters.cc
View File

@ -29,6 +29,7 @@
NEXTPNR_NAMESPACE_BEGIN
namespace {
enum ClusterWireNodeState
{
IN_SINK_SITE = 0,
@ -51,6 +52,7 @@ struct ClusterWireNode
int depth;
bool only_down;
};
} // namespace
static void handle_expansion_node(const Context *ctx, WireId prev_wire, PipId pip, ClusterWireNode curr_node,
std::vector<ClusterWireNode> &nodes_to_expand, pool<BelId> &bels,
@ -678,7 +680,7 @@ void Arch::prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index)
for (auto &cell : macro_to_cells[ci->macro_parent])
for (auto &node : cluster->connection_graph)
if (IdString(node.cell_type) == cell->type)
if (node.idx != 0 && cell->name != ci->name || node.idx == 0 && cell->name == ci->name) {
if ((node.idx != 0 && cell->name != ci->name) || (node.idx == 0 && cell->name == ci->name)) {
idx_to_cells[node.idx].insert(cell);
}
@ -712,7 +714,7 @@ void Arch::prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index)
for (const auto &cell : arc.second)
possible_idx[cell].insert(arc.first);
for (const auto arc : possible_idx) {
for (const auto &arc : possible_idx) {
log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
for (const auto idx : arc.second)
log_info(" - %d\n", idx);
@ -743,7 +745,7 @@ void Arch::prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index)
for (const auto &cell : arc.second)
possible_idx[cell].insert(arc.first);
for (const auto arc : possible_idx) {
for (const auto &arc : possible_idx) {
log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
for (const auto idx : arc.second)
log_info(" - %d\n", idx);
@ -809,7 +811,7 @@ void Arch::prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index)
for (const auto &cell : arc.second)
possible_idx[cell].insert(arc.first);
for (const auto arc : possible_idx) {
for (const auto &arc : possible_idx) {
log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
for (const auto idx : arc.second)
log_info(" - %d\n", idx);
@ -831,7 +833,7 @@ void Arch::prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index)
for (const auto &cell : arc.second)
possible_idx[cell].insert(arc.first);
for (const auto arc : possible_idx) {
for (const auto &arc : possible_idx) {
log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
for (const auto idx : arc.second)
log_info(" - %d\n", idx);

3
fpga_interchange/dedicated_interconnect.cc
View File

@ -23,7 +23,7 @@
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
namespace {
// All legal routes involved at most 2 sites, the source site and the sink
// site. The source site and sink sites may be the same, but that is not
// dedicated routing, that is intra site routing.
@ -51,6 +51,7 @@ struct WireNode
WireNodeState state;
int depth;
};
} // namespace
// Maximum depth that a dedicate interconnect is considered.
//