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Fix LUT input delays, speedup construct_wire_to_delay?

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This commit is contained in:
Eddie Hung 2018-11-11 14:15:11 -08:00
parent 53f025c03f
commit 75654a69f0
2 changed files with 54 additions and 37 deletions
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89
xc7/arch.cc
View File

@ -41,7 +41,7 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
site_index_to_type(construct_site_index_to_type(ctx, sites)), site_index_to_type(construct_site_index_to_type(ctx, sites)),
bel_to_loc(construct_bel_to_loc(sites, tiles, num_bels, site_index_to_type)), bel_to_loc(construct_bel_to_loc(sites, tiles, num_bels, site_index_to_type)),
wire_to_tilewire(construct_wire_to_tilewire(segments, tiles, segment_to_wire, trivial_to_wire)), wire_to_tilewire(construct_wire_to_tilewire(segments, tiles, segment_to_wire, trivial_to_wire)),
num_wires(wire_to_tilewire.size()), wire_to_delay(construct_wire_to_delay(wire_to_tilewire, *ddb)), num_wires(wire_to_tilewire.size()), wire_to_delay(construct_wire_to_delay(tiles, wire_to_tilewire, *ddb)),
pip_to_arc(construct_pip_to_arc(wire_to_tilewire, *ddb, wire_to_pips_uphill, wire_to_pips_downhill)), pip_to_arc(construct_pip_to_arc(wire_to_tilewire, *ddb, wire_to_pips_uphill, wire_to_pips_downhill)),
num_pips(pip_to_arc.size()) num_pips(pip_to_arc.size())
{ {
@ -163,7 +163,7 @@ TorcInfo::construct_wire_to_tilewire(const Segments &segments, const Tiles &tile
wire_to_tilewire.shrink_to_fit(); wire_to_tilewire.shrink_to_fit();
return wire_to_tilewire; return wire_to_tilewire;
} }
std::vector<DelayInfo> TorcInfo::construct_wire_to_delay(const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb) std::vector<DelayInfo> TorcInfo::construct_wire_to_delay(const Tiles &tiles, const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb)
{ {
std::vector<DelayInfo> wire_to_delay; std::vector<DelayInfo> wire_to_delay;
wire_to_delay.reserve(wire_to_tilewire.size()); wire_to_delay.reserve(wire_to_tilewire.size());
@ -174,45 +174,62 @@ std::vector<DelayInfo> TorcInfo::construct_wire_to_delay(const std::vector<Tilew
const boost::regex re_BYP_B = boost::regex("BYP_[BL]\\d"); const boost::regex re_BYP_B = boost::regex("BYP_[BL]\\d");
const boost::regex re_BOUNCE_NS = boost::regex("(BYP|FAN)_BOUNCE_[NS]3_\\d"); const boost::regex re_BOUNCE_NS = boost::regex("(BYP|FAN)_BOUNCE_[NS]3_\\d");
const boost::regex re_FAN = boost::regex("FAN(_ALT)?\\d"); const boost::regex re_FAN = boost::regex("FAN(_ALT)?\\d");
const boost::regex re_CLB_I1_6 = boost::regex("CLBL[LM]_(L|LL|M)_[A-D]([1-6])");
std::unordered_map</*TileTypeIndex*/unsigned, std::vector<delay_t>> delay_lookup;
boost::cmatch what; boost::cmatch what;
ExtendedWireInfo ewi(ddb);
for (const auto &tw : wire_to_tilewire) { for (const auto &tw : wire_to_tilewire) {
ewi.set(tw); const TileInfo& tileInfo = tiles.getTileInfo(tw.getTileIndex());
DelayInfo d; auto tile_type_index = tileInfo.getTypeIndex();
if (boost::regex_match(ewi.mWireName, what, re_124)) {
switch (what.str(2)[0]) { auto it = delay_lookup.find(tile_type_index);
case '1': if (it == delay_lookup.end()) {
d.delay = 150; auto wireCount = tiles.getWireCount(tile_type_index);
break; std::vector<delay_t> tile_delays(wireCount);
case '2': for (WireIndex wireIndex(0); wireIndex < wireCount; wireIndex++) {
d.delay = 170; const WireInfo& wireInfo = tiles.getWireInfo(tile_type_index, wireIndex);
break; auto wire_name = wireInfo.getName();
case '4': if (boost::regex_match(wire_name, what, re_124)) {
d.delay = 210; switch (what.str(2)[0]) {
break; case '1': tile_delays[wireIndex] = 150; break;
case '6': case '2': tile_delays[wireIndex] = 170; break;
d.delay = 210; case '4': tile_delays[wireIndex] = 210; break;
break; case '6': tile_delays[wireIndex] = 210; break;
default: default: throw;
throw; }
} else if (boost::regex_match(wire_name, what, re_L)) {
std::string l(what[2]);
if (l == "H")
tile_delays[wireIndex] = 360;
else if (l == "VB")
tile_delays[wireIndex] = 300;
else if (l == "V")
tile_delays[wireIndex] = 350;
else
throw;
} else if (boost::regex_match(wire_name, what, re_BYP)) {
tile_delays[wireIndex] = 190;
} else if (boost::regex_match(wire_name, what, re_BYP_B)) {
} else if (boost::regex_match(wire_name, what, re_FAN)) {
tile_delays[wireIndex] = 190;
} else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) {
switch (what.str(2)[0]) {
case '1': tile_delays[wireIndex] = 280; break;
case '2': tile_delays[wireIndex] = 280; break;
case '3': tile_delays[wireIndex] = 180; break;
case '4': tile_delays[wireIndex] = 180; break;
case '5': tile_delays[wireIndex] = 80; break;
case '6': tile_delays[wireIndex] = 40; break;
default: throw;
}
}
} }
} else if (boost::regex_match(ewi.mWireName, what, re_L)) { it = delay_lookup.emplace(tile_type_index, std::move(tile_delays)).first;
std::string l(what[2]);
if (l == "H")
d.delay = 360;
else if (l == "VB")
d.delay = 300;
else if (l == "V")
d.delay = 350;
else
throw;
} else if (boost::regex_match(ewi.mWireName, what, re_BYP)) {
d.delay = 190;
} else if (boost::regex_match(ewi.mWireName, what, re_BYP_B)) {
} else if (boost::regex_match(ewi.mWireName, what, re_FAN)) {
d.delay = 190;
} }
assert(it != delay_lookup.end());
DelayInfo d;
d.delay = it->second[tw.getWireIndex()];
wire_to_delay.emplace_back(std::move(d)); wire_to_delay.emplace_back(std::move(d));
} }

2
xc7/arch.h
View File

@ -331,7 +331,7 @@ struct TorcInfo
construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles, construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles,
std::unordered_map<Segments::SegmentReference, int> &segment_to_wire, std::unordered_map<Segments::SegmentReference, int> &segment_to_wire,
std::unordered_map<Tilewire, int> &trivial_to_wire); std::unordered_map<Tilewire, int> &trivial_to_wire);
static std::vector<DelayInfo> construct_wire_to_delay(const std::vector<Tilewire> &wire_to_tilewire, static std::vector<DelayInfo> construct_wire_to_delay(const Tiles &tiles, const std::vector<Tilewire> &wire_to_tilewire,
const DDB &ddb); const DDB &ddb);
static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb, static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb,
std::vector<std::vector<int>> &wire_to_pips_uphill, std::vector<std::vector<int>> &wire_to_pips_uphill,