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Use pass trough signals to validate architecture data

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This commit is contained in:
Miodrag Milanovic 2025-01-22 16:02:55 +01:00
parent e2b3e7e86f
commit 75d684d032
1 changed files with 12 additions and 0 deletions
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12
himbaechel/uarch/gatemate/gen/arch_gen.py
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@ -118,6 +118,18 @@ def main():
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_I1")) pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_I1"))
pp = tt.create_pip("CPE.RAM_I2", "CPE.OUT2") pp = tt.create_pip("CPE.RAM_I2", "CPE.OUT2")
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_I2")) pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_I2"))
#pp = tt.create_pip("CPE.CINX", "CPE.COUTX")
#pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("COUTX"))
#pp = tt.create_pip("CPE.PINX", "CPE.POUTX")
#pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("POUTX"))
#pp = tt.create_pip("CPE.CINY1", "CPE.COUTY1")
#pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("COUTY1"))
#pp = tt.create_pip("CPE.PINY1", "CPE.POUTY1")
#pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("POUTY1"))
#pp = tt.create_pip("CPE.CINY2", "CPE.COUTY2")
#pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("COUTY2"))
#pp = tt.create_pip("CPE.PINY2", "CPE.POUTY2")
#pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("POUTY2"))
for i in range(1,9): for i in range(1,9):
tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE") tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}") pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")