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Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fix

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ice40: Fix propagation of constraints through SB_GB
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myrtle 2022-05-08 13:37:53 +01:00 committed by GitHub
commit 769a1f263a
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1 changed files with 24 additions and 7 deletions
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31
ice40/pack.cc
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@ -671,13 +671,6 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
for (auto &user : keep_users)
user.cell->ports[user.port].user_idx = net->users.add(user);
if (net->clkconstr) {
glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
glbnet->clkconstr->low = net->clkconstr->low;
glbnet->clkconstr->high = net->clkconstr->high;
glbnet->clkconstr->period = net->clkconstr->period;
}
ctx->cells[gb->name] = std::move(gb);
}
@ -803,6 +796,29 @@ static void promote_globals(Context *ctx)
}
}
static void copy_gb_constraints(Context *ctx)
{
// Copy constraints through GBs and PLLs
bool did_something = false;
do {
did_something = false;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (!is_gbuf(ctx, ci))
continue;
NetInfo *in = ci->getPort(id_USER_SIGNAL_TO_GLOBAL_BUFFER);
NetInfo *out = ci->getPort(id_GLOBAL_BUFFER_OUTPUT);
if (in && out && in->clkconstr && !out->clkconstr) {
out->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
out->clkconstr->low = in->clkconstr->low;
out->clkconstr->high = in->clkconstr->high;
out->clkconstr->period = in->clkconstr->period;
did_something = true;
}
}
} while (did_something);
}
// Figure out where to place PLLs
static void place_plls(Context *ctx)
{
@ -1711,6 +1727,7 @@ bool Arch::pack()
pack_plls(ctx);
if (!bool_or_default(ctx->settings, id_no_promote_globals, false))
promote_globals(ctx);
copy_gb_constraints(ctx);
ctx->assignArchInfo();
constrain_chains(ctx);
ctx->fixupHierarchy();