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Merge pull request #1068 from YosysHQ/cleanup_and_sync

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Cleanup and sync
This commit is contained in:
myrtle 2022-12-22 21:19:21 +01:00 committed by GitHub
commit 76fea8268c
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6 changed files with 14 additions and 30 deletions
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3
common/kernel/design_utils.h
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@ -31,9 +31,6 @@ NEXTPNR_NAMESPACE_BEGIN
Utilities for design manipulation, intended for use inside packing algorithms
*/
// Disconnect a net (if connected) from old, and connect it to rep
void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdString rep_name);
// If a net drives a given port of a cell matching a predicate (in many
// cases more than one cell type, e.g. SB_DFFxx so a predicate is used), return
// the first instance of that cell (otherwise nullptr). If exclusive is set to

8
common/kernel/timing.cc
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@ -707,7 +707,7 @@ void TimingAnalyser::print_critical_path(CellPortKey endpoint, domain_id_t domai
ctx->getDelayNS(ports.at(cursor).domain_pairs.at(domain_pair).setup_slack));
while (cursor != CellPortKey()) {
log(" %s.%s (net %s)\n", ctx->nameOf(cursor.cell), ctx->nameOf(cursor.port),
ctx->nameOf(get_net_or_empty(ctx->cells.at(cursor.cell).get(), cursor.port)));
ctx->nameOf(ctx->cells.at(cursor.cell)->getPort(cursor.port)));
if (!ports.at(cursor).arrival.count(dp.key.launch))
break;
cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_max;
@ -865,7 +865,7 @@ struct Timing
topological_order.emplace_back(o->net);
for (int i = 0; i < clocks; i++) {
TimingClockingInfo clkInfo = ctx->getPortClockingInfo(cell.second.get(), o->name, i);
const NetInfo *clknet = get_net_or_empty(cell.second.get(), clkInfo.clock_port);
const NetInfo *clknet = cell.second->getPort(clkInfo.clock_port);
IdString clksig = clknet ? clknet->name : async_clock;
net_data[o->net][ClockEvent{clksig, clknet ? clkInfo.edge : RISING_EDGE}] =
TimingData{clkInfo.clockToQ.maxDelay()};
@ -1125,7 +1125,7 @@ struct Timing
if (portClass == TMG_REGISTER_INPUT) {
for (int i = 0; i < port_clocks; i++) {
TimingClockingInfo clkInfo = ctx->getPortClockingInfo(usr.cell, usr.port, i);
const NetInfo *clknet = get_net_or_empty(usr.cell, clkInfo.clock_port);
const NetInfo *clknet = usr.cell->getPort(clkInfo.clock_port);
IdString clksig = clknet ? clknet->name : async_clock;
process_endpoint(clksig, clknet ? clkInfo.edge : RISING_EDGE, clkInfo.setup.maxDelay());
}
@ -1295,7 +1295,7 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
if (portClass == TMG_REGISTER_OUTPUT) {
for (int i = 0; i < port_clocks; i++) {
TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port);
const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) {
last_port = clockInfo.clock_port;
clock_start = i;

19
common/kernel/util.h
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@ -102,25 +102,6 @@ bool bool_or_default(const Container &ct, const KeyType &key, bool def = false)
return bool(int_or_default(ct, key, int(def)));
};
// Return a net if port exists, or nullptr
inline const NetInfo *get_net_or_empty(const CellInfo *cell, const IdString port)
{
auto found = cell->ports.find(port);
if (found != cell->ports.end())
return found->second.net;
else
return nullptr;
}
inline NetInfo *get_net_or_empty(CellInfo *cell, const IdString port)
{
auto found = cell->ports.find(port);
if (found != cell->ports.end())
return found->second.net;
else
return nullptr;
}
// Get only value from a forward iterator begin/end pair.
//
// Generates assertion failure if std::distance(begin, end) != 1.

7
common/place/placer_heap.cc
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@ -362,7 +362,11 @@ class HeAPPlacer
} else
#endif
{
if (!placer1_refine(ctx, Placer1Cfg(ctx))) {
auto placer1_cfg = Placer1Cfg(ctx);
placer1_cfg.hpwl_scale_x = cfg.hpwl_scale_x;
placer1_cfg.hpwl_scale_y = cfg.hpwl_scale_y;
placer1_cfg.netShareWeight = cfg.netShareWeight;
if (!placer1_refine(ctx, placer1_cfg)) {
return false;
}
}
@ -1813,6 +1817,7 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
criticalityExponent = ctx->setting<int>("placerHeap/criticalityExponent");
timingWeight = ctx->setting<int>("placerHeap/timingWeight");
parallelRefine = ctx->setting<bool>("placerHeap/parallelRefine", false);
netShareWeight = ctx->setting<float>("placerHeap/netShareWeight", 0);
timing_driven = ctx->setting<bool>("timing_driven");
solverTolerance = 1e-5;

1
common/place/placer_heap.h
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@ -41,6 +41,7 @@ struct PlacerHeapCfg
bool timing_driven;
float solverTolerance;
bool placeAllAtOnce;
float netShareWeight;
bool parallelRefine;
int cell_placement_timeout;

6
ecp5/pack.cc
View File

@ -219,7 +219,7 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_ff(ctx, ci)) {
NetInfo *di = get_net_or_empty(ci, id_DI);
NetInfo *di = ci->getPort(id_DI);
if (di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
CellInfo *comb = di->driver.cell;
if (comb->cluster != ClusterId()) {
@ -306,7 +306,7 @@ class Ecp5Packer
// Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
NetInfo *f1 = get_net_or_empty(lut5, id_F1);
NetInfo *f1 = lut5->getPort(id_F1);
NPNR_ASSERT(f1 != nullptr);
NPNR_ASSERT(f1->driver.cell != nullptr);
return f1->driver.cell;
@ -2806,7 +2806,7 @@ bool Arch::pack()
void Arch::assign_arch_info_for_cell(CellInfo *ci)
{
auto get_port_net = [&](CellInfo *ci, IdString p) {
NetInfo *n = get_net_or_empty(ci, p);
NetInfo *n = ci->getPort(p);
return n ? n->name : IdString();
};
if (ci->type == id_TRELLIS_COMB) {