diff --git a/common/kernel/basectx.cc b/common/kernel/basectx.cc index 82cdd835..777d06e1 100644 --- a/common/kernel/basectx.cc +++ b/common/kernel/basectx.cc @@ -26,6 +26,18 @@ NEXTPNR_NAMESPACE_BEGIN +IdString BaseCtx::idf(const char *fmt, ...) const +{ + std::string string; + va_list ap; + + va_start(ap, fmt); + string = vstringf(fmt, ap); + va_end(ap); + + return id(string); +} + const char *BaseCtx::nameOfBel(BelId bel) const { const Context *ctx = getCtx(); diff --git a/common/kernel/basectx.h b/common/kernel/basectx.h index 5775e47f..c8791a2b 100644 --- a/common/kernel/basectx.h +++ b/common/kernel/basectx.h @@ -162,6 +162,8 @@ struct BaseCtx IdString id(const char *s) const { return IdString(this, s); } + IdString idf(const char *fmt, ...) const; // create IdString using printf formatting + Context *getCtx() { return as_ctx; } const Context *getCtx() const { return as_ctx; } diff --git a/common/kernel/nextpnr_types.cc b/common/kernel/nextpnr_types.cc index 8563eb27..6da37763 100644 --- a/common/kernel/nextpnr_types.cc +++ b/common/kernel/nextpnr_types.cc @@ -152,8 +152,8 @@ void CellInfo::movePortBusTo(IdString old_name, int old_offset, bool old_bracket IdString new_name, int new_offset, bool new_brackets, int width) { for (int i = 0; i < width; i++) { - IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset)); - IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset)); + IdString old_port = ctx->idf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset); + IdString new_port = ctx->idf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset); movePortTo(old_port, new_cell, new_port); } } @@ -171,8 +171,8 @@ void CellInfo::copyPortBusTo(IdString old_name, int old_offset, bool old_bracket IdString new_name, int new_offset, bool new_brackets, int width) { for (int i = 0; i < width; i++) { - IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset)); - IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset)); + IdString old_port = ctx->idf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset); + IdString new_port = ctx->idf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset); copyPortTo(old_port, new_cell, new_port); } } diff --git a/ecp5/arch.cc b/ecp5/arch.cc index d98ee54c..0b763612 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -121,17 +121,17 @@ Arch::Arch(ArchArgs args) : args(args) BaseArch::init_bel_buckets(); for (int i = 0; i < chip_info->width; i++) - x_ids.push_back(id(stringf("X%d", i))); + x_ids.push_back(idf("X%d", i)); for (int i = 0; i < chip_info->height; i++) - y_ids.push_back(id(stringf("Y%d", i))); + y_ids.push_back(idf("Y%d", i)); for (int i = 0; i < chip_info->width; i++) { - IdString x_id = id(stringf("X%d", i)); + IdString x_id = idf("X%d", i); x_ids.push_back(x_id); id_to_x[x_id] = i; } for (int i = 0; i < chip_info->height; i++) { - IdString y_id = id(stringf("Y%d", i)); + IdString y_id = idf("Y%d", i); y_ids.push_back(y_id); id_to_y[y_id] = i; } diff --git a/ecp5/pack.cc b/ecp5/pack.cc index 7aa9b4c4..4cd33dee 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -801,7 +801,7 @@ class Ecp5Packer ci->disconnectPort(id_WRE); for (int i = 0; i < 4; i++) - ci->disconnectPort(ctx->id(stringf("RAD[%d]", i))); + ci->disconnectPort(ctx->idf("RAD[%d]", i)); // Setup placement constraints // Use the 0th bit as an anchor diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 6a7c4fe1..3ce9f79e 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -907,7 +907,7 @@ static void prepare_sites_for_routing(Context *ctx) // We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for // Nexus they are the same) so add a prefix to the bel pin name to disambiguate it - IdString cell_pin = ctx->id(stringf("%s_PHYS", ctx->nameOf(bel_pin))); + IdString cell_pin = ctx->idf("%s_PHYS", ctx->nameOf(bel_pin)); PortInfo port_info; port_info.name = cell_pin; diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc index 8f7f8231..cc67833a 100644 --- a/fpga_interchange/macros.cc +++ b/fpga_interchange/macros.cc @@ -45,7 +45,7 @@ static const MacroExpansionPOD *lookup_macro_rules(const ChipInfoPOD *chip, IdSt static IdString derived_name(Context *ctx, IdString base_name, IdString suffix) { - return ctx->id(stringf("%s/%s", base_name.c_str(ctx), suffix.c_str(ctx))); + return ctx->idf("%s/%s", base_name.c_str(ctx), suffix.c_str(ctx)); } void Arch::expand_macros() diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc index 49b36792..987c3236 100644 --- a/generic/viaduct/example/example.cc +++ b/generic/viaduct/example/example.cc @@ -108,24 +108,23 @@ struct ExampleImpl : ViaductAPI auto &w = row_wires.at(x); for (int z = 0; z < N; z++) { // Clock input - w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y)); + w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("CLK%d", z)), ctx->id("CLK"), x, y)); // FF input - w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y)); + w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("D%d", z)), ctx->id("D"), x, y)); // FF and LUT outputs - w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y)); - w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y)); + w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("Q%d", z)), ctx->id("Q"), x, y)); + w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("F%d", z)), ctx->id("F"), x, y)); // LUT inputs for (int i = 0; i < K; i++) - w.i.push_back( - ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y)); + w.i.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("L%dI%d", z, i)), ctx->id("I"), x, y)); } // Local wires for (int l = 0; l < Wl; l++) - w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("LOCAL%d", l))), ctx->id("LOCAL"), x, y)); + w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("LOCAL%d", l)), ctx->id("LOCAL"), x, y)); // Pad wires for IO if (is_io(x, y) && x != y) for (int z = 0; z < 2; z++) - w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y)); + w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("PAD%d", z)), id_PAD, x, y)); } } } @@ -139,7 +138,7 @@ struct ExampleImpl : ViaductAPI { auto &w = wires_by_tile.at(y).at(x); for (int z = 0; z < 2; z++) { - BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false); + BelId b = ctx->addBel(h.xy_id(x, y, ctx->idf("IO%d", z)), id_IOB, Loc(x, y, z), false, false); ctx->addBelInout(b, id_PAD, w.pad.at(z)); ctx->addBelInput(b, id_I, w.i.at(z * K + 0)); ctx->addBelInput(b, id_EN, w.i.at(z * K + 1)); @@ -157,17 +156,16 @@ struct ExampleImpl : ViaductAPI auto &w = wires_by_tile.at(y).at(x); for (int z = 0; z < N; z++) { // Create LUT bel - BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false, - false); + BelId lut = ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_LUT", z)), id_LUT4, Loc(x, y, z * 2), false, false); for (int k = 0; k < K; k++) - ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.i.at(z * K + k)); + ctx->addBelInput(lut, ctx->idf("I[%d]", k), w.i.at(z * K + k)); ctx->addBelOutput(lut, id_F, w.f.at(z)); // FF data can come from LUT output or LUT I3 add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z)); add_pip(Loc(x, y, 0), w.i.at(z * K + (K - 1)), w.d.at(z)); // Create DFF bel - BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1), - false, false); + BelId dff = + ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_FF", z)), id_DFF, Loc(x, y, z * 2 + 1), false, false); ctx->addBelInput(dff, id_CLK, w.clk.at(z)); ctx->addBelInput(dff, id_D, w.d.at(z)); ctx->addBelOutput(dff, id_Q, w.q.at(z)); @@ -254,7 +252,7 @@ struct ExampleImpl : ViaductAPI auto &fc = fast_cell_info.at(ci->flat_index); if (ci->type == id_LUT4) { fc.lut_f = ci->getPort(id_F); - fc.lut_i3_used = (ci->getPort(ctx->id(stringf("I[%d]", K - 1))) != nullptr); + fc.lut_i3_used = (ci->getPort(ctx->idf("I[%d]", K - 1)) != nullptr); } else if (ci->type == id_DFF) { fc.ff_d = ci->getPort(id_D); } diff --git a/generic/viaduct/okami/okami.cc b/generic/viaduct/okami/okami.cc index 864bdb45..8142756f 100644 --- a/generic/viaduct/okami/okami.cc +++ b/generic/viaduct/okami/okami.cc @@ -120,45 +120,45 @@ struct OkamiImpl : ViaductAPI auto &w = row_wires.at(x); for (int z = 0; z < N; z++) { // Clock input - w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y)); + w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("CLK%d", z)), ctx->id("CLK"), x, y)); // FF input - w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y)); + w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("D%d", z)), ctx->id("D"), x, y)); // FF and LUT outputs - w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y)); - w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y)); + w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("Q%d", z)), ctx->id("Q"), x, y)); + w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("F%d", z)), ctx->id("F"), x, y)); // LUT inputs for (int i = 0; i < K; i++) w.slice_inputs.push_back( - ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y)); - w.slice_outputs.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("SLICEOUT[%d]", z))), - ctx->id("SLICEOUT"), x, y)); + ctx->addWire(h.xy_id(x, y, ctx->idf("L%dI%d", z, i)), ctx->id("I"), x, y)); + w.slice_outputs.push_back( + ctx->addWire(h.xy_id(x, y, ctx->idf("SLICEOUT[%d]", z)), ctx->id("SLICEOUT"), x, y)); } // Tile inputs for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) { - w.tile_inputs_north.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEINN[%d]", tile_input))), ctx->id("TILEINN"), x, y)); - w.tile_inputs_east.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEINE[%d]", tile_input))), ctx->id("TILEINE"), x, y)); - w.tile_inputs_south.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEINS[%d]", tile_input))), ctx->id("TILEINS"), x, y)); - w.tile_inputs_west.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEINW[%d]", tile_input))), ctx->id("TILEINW"), x, y)); + w.tile_inputs_north.push_back( + ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINN[%d]", tile_input)), ctx->id("TILEINN"), x, y)); + w.tile_inputs_east.push_back( + ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINE[%d]", tile_input)), ctx->id("TILEINE"), x, y)); + w.tile_inputs_south.push_back( + ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINS[%d]", tile_input)), ctx->id("TILEINS"), x, y)); + w.tile_inputs_west.push_back( + ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINW[%d]", tile_input)), ctx->id("TILEINW"), x, y)); } // Tile outputs for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++) { - w.tile_outputs_north.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEOUTN[%d]", tile_output))), ctx->id("TILEOUTN"), x, y)); - w.tile_outputs_east.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEOUTE[%d]", tile_output))), ctx->id("TILEOUTE"), x, y)); - w.tile_outputs_south.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEOUTS[%d]", tile_output))), ctx->id("TILEOUTS"), x, y)); - w.tile_outputs_west.push_back(ctx->addWire( - h.xy_id(x, y, ctx->id(stringf("TILEOUTW[%d]", tile_output))), ctx->id("TILEOUTW"), x, y)); + w.tile_outputs_north.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTN[%d]", tile_output)), + ctx->id("TILEOUTN"), x, y)); + w.tile_outputs_east.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTE[%d]", tile_output)), + ctx->id("TILEOUTE"), x, y)); + w.tile_outputs_south.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTS[%d]", tile_output)), + ctx->id("TILEOUTS"), x, y)); + w.tile_outputs_west.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTW[%d]", tile_output)), + ctx->id("TILEOUTW"), x, y)); } // Pad wires for IO if (is_io(x, y) && x != y) for (int z = 0; z < 2; z++) - w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y)); + w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("PAD%d", z)), id_PAD, x, y)); } } } @@ -172,7 +172,7 @@ struct OkamiImpl : ViaductAPI { auto &w = wires_by_tile.at(y).at(x); for (int z = 0; z < 2; z++) { - BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false); + BelId b = ctx->addBel(h.xy_id(x, y, ctx->idf("IO%d", z)), id_IOB, Loc(x, y, z), false, false); ctx->addBelInout(b, id_PAD, w.pad.at(z)); ctx->addBelInput(b, id_I, w.slice_inputs.at(z * K + 0)); ctx->addBelInput(b, id_EN, w.slice_inputs.at(z * K + 1)); @@ -190,17 +190,16 @@ struct OkamiImpl : ViaductAPI auto &w = wires_by_tile.at(y).at(x); for (int z = 0; z < N; z++) { // Create LUT bel - BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false, - false); + BelId lut = ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_LUT", z)), id_LUT4, Loc(x, y, z * 2), false, false); for (int k = 0; k < K; k++) - ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.slice_inputs.at(z * K + k)); + ctx->addBelInput(lut, ctx->idf("I[%d]", k), w.slice_inputs.at(z * K + k)); ctx->addBelOutput(lut, id_F, w.f.at(z)); // FF data can come from LUT output or LUT I3 add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z)); add_pip(Loc(x, y, 0), w.slice_inputs.at(z * K + (K - 1)), w.d.at(z)); // Create DFF bel - BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1), - false, false); + BelId dff = + ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_FF", z)), id_DFF, Loc(x, y, z * 2 + 1), false, false); ctx->addBelInput(dff, id_CLK, w.clk.at(z)); ctx->addBelInput(dff, id_D, w.d.at(z)); ctx->addBelOutput(dff, id_Q, w.q.at(z)); @@ -495,7 +494,7 @@ struct OkamiImpl : ViaductAPI auto &fc = fast_cell_info.at(ci->flat_index); if (ci->type == id_LUT4) { fc.lut_f = ci->getPort(id_F); - fc.lut_i3_used = (ci->getPort(ctx->id(stringf("I[%d]", K - 1))) != nullptr); + fc.lut_i3_used = (ci->getPort(ctx->idf("I[%d]", K - 1)) != nullptr); } else if (ci->type == id_DFF) { fc.ff_d = ci->getPort(id_D); } diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc index 153d2a0e..53df625c 100644 --- a/generic/viaduct_helpers.cc +++ b/generic/viaduct_helpers.cc @@ -29,15 +29,15 @@ void ViaductHelpers::resize_ids(int x, int y, int z) { NPNR_ASSERT(x >= 0 && y >= 0 && x <= 20000 && y <= 20000 && z <= 1000); while (int(x_ids.size()) <= x) { - IdString next = ctx->id(stringf("X%d", int(x_ids.size()))); + IdString next = ctx->idf("X%d", int(x_ids.size())); x_ids.push_back(next); } while (int(y_ids.size()) <= y) { - IdString next = ctx->id(stringf("Y%d", int(y_ids.size()))); + IdString next = ctx->idf("Y%d", int(y_ids.size())); y_ids.push_back(next); } while (int(z_ids.size()) <= y) { - IdString next = ctx->id(stringf("Z%d", int(z_ids.size()))); + IdString next = ctx->idf("Z%d", int(z_ids.size())); z_ids.push_back(next); } } diff --git a/gowin/pack.cc b/gowin/pack.cc index 4b5bc81d..d978ac40 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -733,7 +733,7 @@ void pack_sram(Context *ctx) // ci->disconnectPort(id_WRE); for (int i = 0; i < 4; i++) - ci->disconnectPort(ctx->id(stringf("RAD[%d]", i))); + ci->disconnectPort(ctx->idf("RAD[%d]", i)); // Setup placement constraints // Use the 0th bit as an anchor diff --git a/ice40/arch.cc b/ice40/arch.cc index 6746b302..905b8d61 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -111,12 +111,12 @@ Arch::Arch(ArchArgs args) : args(args) log_error("Unsupported package '%s'.\n", args.package.c_str()); for (int i = 0; i < chip_info->width; i++) { - IdString x_id = id(stringf("X%d", i)); + IdString x_id = idf("X%d", i); x_ids.push_back(x_id); id_to_x[x_id] = i; } for (int i = 0; i < chip_info->height; i++) { - IdString y_id = id(stringf("Y%d", i)); + IdString y_id = idf("Y%d", i); y_ids.push_back(y_id); id_to_y[y_id] = i; } diff --git a/machxo2/arch.cc b/machxo2/arch.cc index 5fcdeaf7..b1a4a62a 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -93,17 +93,17 @@ Arch::Arch(ArchArgs args) : args(args) BaseArch::init_bel_buckets(); for (int i = 0; i < chip_info->width; i++) - x_ids.push_back(id(stringf("X%d", i))); + x_ids.push_back(idf("X%d", i)); for (int i = 0; i < chip_info->height; i++) - y_ids.push_back(id(stringf("Y%d", i))); + y_ids.push_back(idf("Y%d", i)); for (int i = 0; i < chip_info->width; i++) { - IdString x_id = id(stringf("X%d", i)); + IdString x_id = idf("X%d", i); x_ids.push_back(x_id); id_to_x[x_id] = i; } for (int i = 0; i < chip_info->height; i++) { - IdString y_id = id(stringf("Y%d", i)); + IdString y_id = idf("Y%d", i); y_ids.push_back(y_id); id_to_y[y_id] = i; } diff --git a/mistral/arch.cc b/mistral/arch.cc index 46ed4f62..4023f5c3 100644 --- a/mistral/arch.cc +++ b/mistral/arch.cc @@ -88,7 +88,7 @@ Arch::Arch(ArchArgs args) // Setup fast identifier maps for (int i = 0; i < 1024; i++) { - IdString int_id = id(stringf("%d", i)); + IdString int_id = idf("%d", i); int2id.push_back(int_id); id2int[int_id] = i; } diff --git a/mistral/globals.cc b/mistral/globals.cc index 1ba70919..6af8920d 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -30,7 +30,7 @@ void Arch::create_clkbuf(int x, int y) continue; // TODO: why do other Zs not work? // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO - BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); + BelId bel = add_bel(x, y, idf("CLKBUF[%d]", z), id_MISTRAL_CLKENA); add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z)); add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT)); // TODO: enable pin @@ -48,9 +48,9 @@ void Arch::create_hps_mpu_general_purpose(int x, int y) BelId gp_bel = add_bel(x, y, id_cyclonev_hps_interface_mpu_general_purpose, id_cyclonev_hps_interface_mpu_general_purpose); for (int i = 0; i < 32; i++) { - add_bel_pin(gp_bel, id(stringf("gp_in[%d]", i)), PORT_IN, + add_bel_pin(gp_bel, idf("gp_in[%d]", i), PORT_IN, get_port(CycloneV::HPS_MPU_GENERAL_PURPOSE, x, y, -1, CycloneV::GP_IN, i)); - add_bel_pin(gp_bel, id(stringf("gp_out[%d]", i)), PORT_OUT, + add_bel_pin(gp_bel, idf("gp_out[%d]", i), PORT_OUT, get_port(CycloneV::HPS_MPU_GENERAL_PURPOSE, x, y, -1, CycloneV::GP_OUT, i)); } } diff --git a/mistral/io.cc b/mistral/io.cc index c8d0238d..6690fc16 100644 --- a/mistral/io.cc +++ b/mistral/io.cc @@ -27,8 +27,8 @@ void Arch::create_gpio(int x, int y) { for (int z = 0; z < 4; z++) { // Notional pad wire - WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z))); - BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO); + WireId pad = add_wire(x, y, idf("PAD[%d]", z)); + BelId bel = add_bel(x, y, idf("IO[%d]", z), id_MISTRAL_IO); add_bel_pin(bel, id_PAD, PORT_INOUT, pad); if (has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) { // FIXME: is the port index of zero always correct? diff --git a/mistral/lab.cc b/mistral/lab.cc index 4b66ed0c..d65ccf53 100644 --- a/mistral/lab.cc +++ b/mistral/lab.cc @@ -37,10 +37,10 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) // Create the control set and E/F selection - which is per pair of FF for (int i = 0; i < 2; i++) { // Wires - alm.sel_clk[i] = arch->add_wire(x, y, arch->id(stringf("CLK%c[%d]", i ? 'B' : 'T', z))); - alm.sel_ena[i] = arch->add_wire(x, y, arch->id(stringf("ENA%c[%d]", i ? 'B' : 'T', z))); - alm.sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z))); - alm.sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z))); + alm.sel_clk[i] = arch->add_wire(x, y, arch->idf("CLK%c[%d]", i ? 'B' : 'T', z)); + alm.sel_ena[i] = arch->add_wire(x, y, arch->idf("ENA%c[%d]", i ? 'B' : 'T', z)); + alm.sel_aclr[i] = arch->add_wire(x, y, arch->idf("ACLR%c[%d]", i ? 'B' : 'T', z)); + alm.sel_ef[i] = arch->add_wire(x, y, arch->idf("%cEF[%d]", i ? 'B' : 'T', z)); // Muxes - three CLK/ENA per LAB, two ACLR for (int j = 0; j < 3; j++) { arch->add_pip(lab.clk_wires[j], alm.sel_clk[i]); @@ -72,20 +72,20 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) } } else { // Output from last combinational unit - carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1))); - share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1))); + carry_in = arch->add_wire(x, y, arch->idf("CARRY[%d]", (z * 2 + i) - 1)); + share_in = arch->add_wire(x, y, arch->idf("SHARE[%d]", (z * 2 + i) - 1)); } if (z == 9 && i == 1) { carry_out = arch->add_wire(x, y, id_CO); share_out = arch->add_wire(x, y, id_SHAREOUT); } else { - carry_out = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", z * 2 + i))); - share_out = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", z * 2 + i))); + carry_out = arch->add_wire(x, y, arch->idf("CARRY[%d]", z * 2 + i)); + share_out = arch->add_wire(x, y, arch->idf("SHARE[%d]", z * 2 + i)); } - BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_COMB%d", z, i)), - lab.is_mlab ? id_MISTRAL_MCOMB : id_MISTRAL_COMB); + BelId bel = + arch->add_bel(x, y, arch->idf("ALM%d_COMB%d", z, i), lab.is_mlab ? id_MISTRAL_MCOMB : id_MISTRAL_COMB); // LUT/MUX inputs arch->add_bel_pin(bel, id_A, PORT_IN, arch->get_port(block_type, x, y, z, CycloneV::A)); arch->add_bel_pin(bel, id_B, PORT_IN, arch->get_port(block_type, x, y, z, CycloneV::B)); @@ -101,7 +101,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) arch->add_bel_pin(bel, id_CO, PORT_OUT, carry_out); arch->add_bel_pin(bel, id_SHAREOUT, PORT_OUT, share_out); // Combinational output - alm.comb_out[i] = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i))); + alm.comb_out[i] = arch->add_wire(x, y, arch->idf("COMBOUT[%d]", z * 2 + i)); arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, alm.comb_out[i]); if (lab.is_mlab) { // Write address - shared between all ALMs in a LAB @@ -128,11 +128,11 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) for (int i = 0; i < 4; i++) { // FF input, selected by *PKREG* - alm.ff_in[i] = arch->add_wire(x, y, arch->id(stringf("FFIN[%d]", (z * 4) + i))); + alm.ff_in[i] = arch->add_wire(x, y, arch->idf("FFIN[%d]", (z * 4) + i)); arch->add_pip(alm.comb_out[i / 2], alm.ff_in[i]); arch->add_pip(alm.sel_ef[i / 2], alm.ff_in[i]); // FF bel - BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_FF%d", z, i)), id_MISTRAL_FF); + BelId bel = arch->add_bel(x, y, arch->idf("ALM%d_FF%d", z, i), id_MISTRAL_FF); arch->add_bel_pin(bel, id_CLK, PORT_IN, alm.sel_clk[i / 2]); arch->add_bel_pin(bel, id_ENA, PORT_IN, alm.sel_ena[i / 2]); arch->add_bel_pin(bel, id_ACLR, PORT_IN, alm.sel_aclr[i / 2]); @@ -142,7 +142,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx) arch->add_bel_pin(bel, id_SDATA, PORT_IN, alm.sel_ef[i / 2]); // FF output - alm.ff_out[i] = arch->add_wire(x, y, arch->id(stringf("FFOUT[%d]", (z * 4) + i))); + alm.ff_out[i] = arch->add_wire(x, y, arch->idf("FFOUT[%d]", (z * 4) + i)); arch->add_bel_pin(bel, id_Q, PORT_OUT, alm.ff_out[i]); // Output mux (*DFF*) WireId out = arch->get_port(block_type, x, y, z, outputs[i]); @@ -182,7 +182,7 @@ void Arch::create_lab(int x, int y, bool is_mlab) // Clocks - hardcode to CLKA choices, as both CLKA and CLKB coming from general routing causes unexpected // permutations for (int i = 0; i < 3; i++) { - lab.clk_wires[i] = add_wire(x, y, id(stringf("CLK%d", i))); + lab.clk_wires[i] = add_wire(x, y, idf("CLK%d", i)); add_pip(get_port(block_type, x, y, -1, CycloneV::CLKIN, 0), lab.clk_wires[i]); // dedicated routing add_pip(get_port(block_type, x, y, -1, CycloneV::DATAIN, 0), lab.clk_wires[i]); // general routing } @@ -278,7 +278,7 @@ void Arch::assign_comb_info(CellInfo *cell) const cell->combInfo.lut_input_count = 5; cell->combInfo.lut_bits_count = 32; for (int i = 0; i < 5; i++) - cell->combInfo.lut_in[i] = cell->getPort(id(stringf("B1ADDR[%d]", i))); + cell->combInfo.lut_in[i] = cell->getPort(idf("B1ADDR[%d]", i)); auto key = get_mlab_key(cell); cell->combInfo.mlab_group = mlab_groups(key); cell->combInfo.comb_out = cell->getPort(id_B1DATA); @@ -797,8 +797,8 @@ static void assign_mlab_inputs(Context *ctx, CellInfo *cell, int lut) std::array raddr_pins{id_A, id_B, id_C, id_D, id_F0}; for (int i = 0; i < 5; i++) { - cell->pin_data[ctx->id(stringf("A1ADDR[%d]", i))].bel_pins = {ctx->id(stringf("WA%d", i))}; - cell->pin_data[ctx->id(stringf("B1ADDR[%d]", i))].bel_pins = {raddr_pins.at(i)}; + cell->pin_data[ctx->idf("A1ADDR[%d]", i)].bel_pins = {ctx->idf("WA%d", i)}; + cell->pin_data[ctx->idf("B1ADDR[%d]", i)].bel_pins = {raddr_pins.at(i)}; } } @@ -918,7 +918,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm) CellInfo *ff = ffs[i * 2 + j]; if (!ff || !ff->ffInfo.datain || alm_data.l6_mode) continue; - CellInfo *rt_lut = createCell(id(stringf("%s$ROUTETHRU", nameOf(ff))), id_MISTRAL_BUF); + CellInfo *rt_lut = createCell(idf("%s$ROUTETHRU", nameOf(ff)), id_MISTRAL_BUF); rt_lut->addInput(id_A); rt_lut->addOutput(id_Q); // Disconnect the original data input to the FF, and connect it to the route-thru LUT instead diff --git a/mistral/m10k.cc b/mistral/m10k.cc index 4da1204f..df44c663 100644 --- a/mistral/m10k.cc +++ b/mistral/m10k.cc @@ -27,34 +27,28 @@ void Arch::create_m10k(int x, int y) add_bel_pin(bel, id_ADDRSTALLA, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0)); add_bel_pin(bel, id_ADDRSTALLB, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0)); for (int z = 0; z < 2; z++) { - add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN, + add_bel_pin(bel, idf("BYTEENABLEA[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z)); - add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN, + add_bel_pin(bel, idf("BYTEENABLEB[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z)); - add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z)); - add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z)); - add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z)); - add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z)); - add_bel_pin(bel, id(stringf("CLKIN[%d]", z + 6)), PORT_IN, - get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6)); + add_bel_pin(bel, idf("ACLR[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z)); + add_bel_pin(bel, idf("RDEN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z)); + add_bel_pin(bel, idf("WREN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z)); + add_bel_pin(bel, idf("CLKIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z)); + add_bel_pin(bel, idf("CLKIN[%d]", z + 6), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6)); } for (int z = 0; z < 4; z++) { - add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN, - get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z)); + add_bel_pin(bel, idf("ENABLE[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z)); } for (int z = 0; z < 12; z++) { - add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z)); - add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z)); + add_bel_pin(bel, idf("ADDRA[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z)); + add_bel_pin(bel, idf("ADDRB[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z)); } for (int z = 0; z < 20; z++) { - add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN, - get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z)); - add_bel_pin(bel, id(stringf("DATABIN[%d]", z)), PORT_IN, - get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z)); - add_bel_pin(bel, id(stringf("DATAAOUT[%d]", z)), PORT_OUT, - get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z)); - add_bel_pin(bel, id(stringf("DATABOUT[%d]", z)), PORT_OUT, - get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z)); + add_bel_pin(bel, idf("DATAAIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z)); + add_bel_pin(bel, idf("DATABIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z)); + add_bel_pin(bel, idf("DATAAOUT[%d]", z), PORT_OUT, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z)); + add_bel_pin(bel, idf("DATABOUT[%d]", z), PORT_OUT, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z)); } } diff --git a/mistral/pack.cc b/mistral/pack.cc index 27ad3c92..709479a2 100644 --- a/mistral/pack.cc +++ b/mistral/pack.cc @@ -417,10 +417,8 @@ struct MistralPacker bit_offset = 1; } for (int bit = bit_offset; bit < abits; bit++) { - ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = { - ctx->id(stringf("ADDRA[%d]", bit + addr_offset))}; - ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = { - ctx->id(stringf("ADDRB[%d]", bit + addr_offset))}; + ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset)}; + ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset)}; } // Data lines @@ -451,13 +449,12 @@ struct MistralPacker } for (int bit = 0; bit < dbits; bit++) { for (int offset : offsets) { - ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back( - ctx->id(stringf("DATAAIN[%d]", bit + offset))); + ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATAAIN[%d]", bit + offset)); } } for (int bit = 0; bit < dbits; bit++) { - ci->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))}; + ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit)}; } } } diff --git a/nexus/arch.cc b/nexus/arch.cc index 9679c3fb..b2ae22ce 100644 --- a/nexus/arch.cc +++ b/nexus/arch.cc @@ -125,12 +125,12 @@ Arch::Arch(ArchArgs args) : args(args) } for (int i = 0; i < chip_info->width; i++) { - IdString x_id = id(stringf("X%d", i)); + IdString x_id = idf("X%d", i); x_ids.push_back(x_id); id_to_x[x_id] = i; } for (int i = 0; i < chip_info->height; i++) { - IdString y_id = id(stringf("Y%d", i)); + IdString y_id = idf("Y%d", i); y_ids.push_back(y_id); id_to_y[y_id] = i; } @@ -377,7 +377,7 @@ IdStringList Arch::getPipName(PipId pip) const { NPNR_ASSERT(pip != PipId()); std::array ids{x_ids.at(pip.tile % chip_info->width), y_ids.at(pip.tile / chip_info->width), - id(stringf("%d", pip.index)), IdString(loc_data(pip).wires[pip_data(pip).to_wire].name), + idf("%d", pip.index), IdString(loc_data(pip).wires[pip_data(pip).to_wire].name), IdString(loc_data(pip).wires[pip_data(pip).from_wire].name)}; return IdStringList(ids); } @@ -784,7 +784,7 @@ bool Arch::route() CellPinMux Arch::get_cell_pinmux(const CellInfo *cell, IdString pin) const { - IdString param = id(stringf("%sMUX", pin.c_str(this))); + IdString param = idf("%sMUX", pin.c_str(this)); auto fnd_param = cell->params.find(param); if (fnd_param == cell->params.end()) return PINMUX_SIG; @@ -805,7 +805,7 @@ CellPinMux Arch::get_cell_pinmux(const CellInfo *cell, IdString pin) const void Arch::set_cell_pinmux(CellInfo *cell, IdString pin, CellPinMux state) { - IdString param = id(stringf("%sMUX", pin.c_str(this))); + IdString param = idf("%sMUX", pin.c_str(this)); switch (state) { case PINMUX_SIG: cell->params.erase(param); diff --git a/nexus/fasm.cc b/nexus/fasm.cc index de03fb82..48a3d259 100644 --- a/nexus/fasm.cc +++ b/nexus/fasm.cc @@ -595,7 +595,7 @@ struct NexusFasmWriter if (wid > 0) { push(stringf("IP_EBR_WID%d", wid)); for (int i = 0; i < 64; i++) { - IdString param = ctx->id(stringf("INITVAL_%02X", i)); + IdString param = ctx->idf("INITVAL_%02X", i); if (!cell->params.count(param)) continue; auto &prop = cell->params.at(param); @@ -906,7 +906,7 @@ struct NexusFasmWriter l.x = 1; push(stringf("IP_LRAM_CORE_R%dC%d", l.y, l.x)); for (int i = 0; i < 128; i++) { - IdString param = ctx->id(stringf("INITVAL_%02X", i)); + IdString param = ctx->idf("INITVAL_%02X", i); if (!cell->params.count(param)) continue; auto &prop = cell->params.at(param); diff --git a/nexus/pack.cc b/nexus/pack.cc index 15752171..0aa61144 100644 --- a/nexus/pack.cc +++ b/nexus/pack.cc @@ -316,8 +316,8 @@ struct NexusPacker return z; } - NetInfo *new_net = ctx->createNet(ctx->id(stringf("$CONST_%s_NET_", type.c_str(ctx)))); - CellInfo *new_cell = ctx->createCell(ctx->id(stringf("$CONST_%s_DRV_", type.c_str(ctx))), type); + NetInfo *new_net = ctx->createNet(ctx->idf("$CONST_%s_NET_", type.c_str(ctx))); + CellInfo *new_cell = ctx->createCell(ctx->idf("$CONST_%s_DRV_", type.c_str(ctx)), type); new_cell->addOutput(id_Z); new_cell->connectPort(id_Z, new_net); return new_net; @@ -823,10 +823,10 @@ struct NexusPacker Tpred pred) { // Create the buffered net - NetInfo *buffered_net = ctx->createNet(ctx->id(stringf("%s$%s", ctx->nameOf(net), name_postfix.c_str()))); + NetInfo *buffered_net = ctx->createNet(ctx->idf("%s$%s", ctx->nameOf(net), name_postfix.c_str())); // Create the buffer cell - CellInfo *buffer = ctx->createCell( - ctx->id(stringf("%s$drv_%s", ctx->nameOf(buffered_net), ctx->nameOf(buffer_type))), buffer_type); + CellInfo *buffer = ctx->createCell(ctx->idf("%s$drv_%s", ctx->nameOf(buffered_net), ctx->nameOf(buffer_type)), + buffer_type); buffer->addInput(i); buffer->addOutput(o); // Drive the buffered net with the buffer @@ -915,9 +915,9 @@ struct NexusPacker } // Get a bus port name - IdString bus(const std::string &base, int i) { return ctx->id(stringf("%s[%d]", base.c_str(), i)); } + IdString bus(const std::string &base, int i) { return ctx->idf("%s[%d]", base.c_str(), i); } - IdString bus_flat(const std::string &base, int i) { return ctx->id(stringf("%s%d", base.c_str(), i)); } + IdString bus_flat(const std::string &base, int i) { return ctx->idf("%s%d", base.c_str(), i); } // Pack a LUTRAM into COMB and RAMW cells void pack_lutram() @@ -939,11 +939,10 @@ struct NexusPacker for (CellInfo *ci : lutrams) { // Create constituent cells - CellInfo *ramw = ctx->createCell(ctx->id(stringf("%s$lutram_ramw$", ctx->nameOf(ci))), id_RAMW); + CellInfo *ramw = ctx->createCell(ctx->idf("%s$lutram_ramw$", ctx->nameOf(ci)), id_RAMW); std::vector combs; for (int i = 0; i < 4; i++) - combs.push_back( - ctx->createCell(ctx->id(stringf("%s$lutram_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB)); + combs.push_back(ctx->createCell(ctx->idf("%s$lutram_comb[%d]$", ctx->nameOf(ci), i), id_OXIDE_COMB)); // Rewiring - external WCK and WRE ci->movePortTo(id_WCK, ramw, id_CLK); ci->movePortTo(id_WRE, ramw, id_LSR); @@ -951,8 +950,8 @@ struct NexusPacker // Internal WCK and WRE signals ramw->addOutput(id_WCKO); ramw->addOutput(id_WREO); - NetInfo *int_wck = ctx->createNet(ctx->id(stringf("%s$lutram_wck$", ctx->nameOf(ci)))); - NetInfo *int_wre = ctx->createNet(ctx->id(stringf("%s$lutram_wre$", ctx->nameOf(ci)))); + NetInfo *int_wck = ctx->createNet(ctx->idf("%s$lutram_wck$", ctx->nameOf(ci))); + NetInfo *int_wre = ctx->createNet(ctx->idf("%s$lutram_wre$", ctx->nameOf(ci))); ramw->connectPort(id_WCKO, int_wck); ramw->connectPort(id_WREO, int_wre); @@ -977,7 +976,7 @@ struct NexusPacker ci->disconnectPort(bus("RAD", i)); } // Write address - internal - NetInfo *int_wad = ctx->createNet(ctx->id(stringf("%s$lutram_wad[%d]$", ctx->nameOf(ci), i))); + NetInfo *int_wad = ctx->createNet(ctx->idf("%s$lutram_wad[%d]$", ctx->nameOf(ci), i)); ramw->addOutput(bus_flat("WADO", i)); ramw->connectPort(bus_flat("WADO", i), int_wad); for (int j = 0; j < 4; j++) { @@ -985,7 +984,7 @@ struct NexusPacker combs[j]->connectPort(bus_flat("WAD", i), int_wad); } // Write data - internal - NetInfo *int_wd = ctx->createNet(ctx->id(stringf("%s$lutram_wd[%d]$", ctx->nameOf(ci), i))); + NetInfo *int_wd = ctx->createNet(ctx->idf("%s$lutram_wd[%d]$", ctx->nameOf(ci), i)); ramw->addOutput(bus_flat("WDO", i)); ramw->connectPort(bus_flat("WDO", i), int_wd); combs[i]->addInput(id_WDI); @@ -1256,8 +1255,7 @@ struct NexusPacker for (CellInfo *ci : widefns) { std::vector combs; for (int i = 0; i < 2; i++) - combs.push_back( - ctx->createCell(ctx->id(stringf("%s$widefn_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB)); + combs.push_back(ctx->createCell(ctx->idf("%s$widefn_comb[%d]$", ctx->nameOf(ci), i), id_OXIDE_COMB)); for (int i = 0; i < 2; i++) { ci->movePortTo(bus_flat("A", i), combs[i], id_A); @@ -1269,7 +1267,7 @@ struct NexusPacker ci->movePortTo(id_SEL, combs[0], id_SEL); ci->movePortTo(id_Z, combs[0], id_OFX); - NetInfo *f1 = ctx->createNet(ctx->id(stringf("%s$widefn_f1$", ctx->nameOf(ci)))); + NetInfo *f1 = ctx->createNet(ctx->idf("%s$widefn_f1$", ctx->nameOf(ci))); combs[0]->addInput(id_F1); combs[1]->addOutput(id_F); combs[1]->connectPort(id_F, f1); @@ -1313,8 +1311,7 @@ struct NexusPacker // Split the carry into two COMB cells std::vector combs; for (int i = 0; i < 2; i++) - combs.push_back( - ctx->createCell(ctx->id(stringf("%s$ccu2_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB)); + combs.push_back(ctx->createCell(ctx->idf("%s$ccu2_comb[%d]$", ctx->nameOf(ci), i), id_OXIDE_COMB)); // Rewire LUT ports for (int i = 0; i < 2; i++) { combs[i]->params[id_MODE] = std::string("CCU2"); @@ -1336,7 +1333,7 @@ struct NexusPacker combs[1]->params[id_INIT] = ctx->parse_lattice_param_from_cell(ci, id_INIT1, 16, 0); // Internal carry net between the two split COMB cells - NetInfo *int_cy = ctx->createNet(ctx->id(stringf("%s$widefn_int_cy$", ctx->nameOf(ci)))); + NetInfo *int_cy = ctx->createNet(ctx->idf("%s$widefn_int_cy$", ctx->nameOf(ci))); combs[0]->addOutput(id_FCO); combs[1]->addInput(id_FCI); combs[0]->connectPort(id_FCO, int_cy); @@ -1550,7 +1547,7 @@ struct NexusPacker // Create a DSP cell CellInfo *create_dsp_cell(IdString base_name, IdString type, CellInfo *constr_base, int dx, int dz) { - IdString name = ctx->id(stringf("%s/%s_x%d_z%d", ctx->nameOf(base_name), ctx->nameOf(type), dx, dz)); + IdString name = ctx->idf("%s/%s_x%d_z%d", ctx->nameOf(base_name), ctx->nameOf(type), dx, dz); CellInfo *cell = ctx->createCell(name, type); if (constr_base != nullptr) { // We might be constraining against an already-constrained cell @@ -1739,10 +1736,10 @@ struct NexusPacker if (mt.wide > 0) { // Dot-product mode special case - ci->copyPortBusTo(ctx->id(stringf("B%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, preadd9[i], - id_B, 0, false, 9); - ci->copyPortBusTo(ctx->id(stringf("A%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, mult9[i], - id_A, 0, false, 9); + ci->copyPortBusTo(ctx->idf("B%d", (i * 9) / mt.wide), (i * 9) % mt.wide, true, preadd9[i], id_B, 0, + false, 9); + ci->copyPortBusTo(ctx->idf("A%d", (i * 9) / mt.wide), (i * 9) % mt.wide, true, mult9[i], id_A, 0, + false, 9); ci->copyPortTo(id_CLK, mult9[i], id_CLK); ci->copyPortTo((i > 1) ? id_CEA2A3 : id_CEA0A1, mult9[i], id_CEA); ci->copyPortTo((i > 1) ? id_RSTA2A3 : id_RSTA0A1, mult9[i], id_RSTA); @@ -1750,8 +1747,8 @@ struct NexusPacker ci->copyPortTo((i > 1) ? id_CEB2B3 : id_CEB0B1, preadd9[i], id_CEB); ci->copyPortTo((i > 1) ? id_RSTB2B3 : id_RSTB0B1, preadd9[i], id_RSTB); // Copy register configuration - copy_param(ci, ctx->id(stringf("REGINPUTAB%d", i)), mult9[i], id_REGBYPSA1); - copy_param(ci, ctx->id(stringf("REGINPUTAB%d", i)), preadd9[i], id_REGBYPSBR0); + copy_param(ci, ctx->idf("REGINPUTAB%d", i), mult9[i], id_REGBYPSA1); + copy_param(ci, ctx->idf("REGINPUTAB%d", i), preadd9[i], id_REGBYPSBR0); } else { // B input split across pre-adders ci->copyPortBusTo(id_B, b_start, true, preadd9[i], id_B, 0, false, 9);