fpga_interchange: tests: add cmake functions
Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
6a08b0d733
commit
77ffdd7fd4
@ -1,8 +0,0 @@
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DESIGN := wire
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DESIGN_TOP := top
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PACKAGE := csg324
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include ../template.mk
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build/wire.json: wire.v | build
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yosys -c run.tcl
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@ -1,8 +0,0 @@
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DESIGN := counter
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DESIGN_TOP := top
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PACKAGE := cpg236
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include ../template.mk
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build/counter.json: counter.v | build
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yosys -c run.tcl
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@ -1,8 +0,0 @@
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DESIGN := ff
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DESIGN_TOP := top
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PACKAGE := csg324
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include ../template.mk
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build/ff.json: ff.v | build
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yosys -c run.tcl
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@ -1,8 +0,0 @@
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DESIGN := lut
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DESIGN_TOP := top
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PACKAGE := csg324
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include ../template.mk
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build/lut.json: lut.v | build
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yosys -c run.tcl
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115
fpga_interchange/examples/tests.cmake
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115
fpga_interchange/examples/tests.cmake
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@ -0,0 +1,115 @@
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function(add_interchange_test)
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# ~~~
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# add_interchange_test(
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# name <name>
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# part <part>
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# part <package>
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# tcl <tcl>
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# xdc <xdc>
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# top <top name>
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# sources <sources list>
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# )
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# ~~~
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set(options)
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set(oneValueArgs name part package tcl xdc top)
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set(multiValueArgs sources)
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cmake_parse_arguments(
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add_interchange_test
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"${options}"
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"${oneValueArgs}"
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"${multiValueArgs}"
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${ARGN}
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)
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set(name ${add_interchange_test_name})
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set(part ${add_interchange_test_part})
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set(package ${add_interchange_test_package})
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set(top ${add_interchange_test_top})
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set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
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set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
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set(sources)
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foreach(source ${add_interchange_test_sources})
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list(APPEND sources ${CMAKE_CURRENT_SOURCE_DIR}/${source})
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endforeach()
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if (NOT DEFINED top)
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# Setting default top value
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set(top "top")
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endif()
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# Synthesis
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set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
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add_custom_command(
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OUTPUT ${synth_json}
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COMMAND
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SOURCES=${sources}
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OUT_JSON=${synth_json}
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yosys -c ${tcl}
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DEPENDS ${sources}
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)
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add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json})
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# Logical Netlist
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set(device_target constraints-luts-${part}-device)
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get_property(device_loc TARGET constraints-luts-${part}-device PROPERTY LOCATION)
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set(netlist ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist)
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add_custom_command(
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OUTPUT ${netlist}
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COMMAND
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python3 -mfpga_interchange.yosys_json
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--device ${device_loc}
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--top ${top}
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${synth_json}
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${netlist}
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DEPENDS
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${synth_json}
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${device_target}
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)
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add_custom_target(test-${family}-${name}-netlist DEPENDS ${netlist})
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set(chipdb_target chipdb-${part}-bba)
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# Physical Netlist
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set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys)
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add_custom_command(
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OUTPUT ${phys}
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COMMAND
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nextpnr-fpga_interchange
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--chipdb ${chipdb_dir}/chipdb-${part}.bba
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--xdc ${xdc}
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--netlist ${netlist}
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--phys ${phys}
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--package ${package}
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DEPENDS
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${netlist}
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${chipdb_target}
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)
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add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})
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set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
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add_custom_command(
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OUTPUT ${dcp}
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COMMAND
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RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
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${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh
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com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
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${netlist} ${phys} ${xdc} ${dcp}
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DEPENDS
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${phys}
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${netlist}
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)
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add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
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add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
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endfunction()
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add_custom_target(all-${family}-tests)
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add_subdirectory(${family}/examples/tests)
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5
fpga_interchange/examples/tests/CMakeLists.txt
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5
fpga_interchange/examples/tests/CMakeLists.txt
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@ -0,0 +1,5 @@
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add_subdirectory(wire)
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add_subdirectory(const_wire)
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add_subdirectory(counter)
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add_subdirectory(ff)
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add_subdirectory(lut)
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17
fpga_interchange/examples/tests/const_wire/CMakeLists.txt
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17
fpga_interchange/examples/tests/const_wire/CMakeLists.txt
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@ -0,0 +1,17 @@
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add_interchange_test(
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name const_wire_basys3
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part xc7a35tcpg236-1
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package cpg236
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tcl run.tcl
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xdc wire.xdc
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sources wire.v
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)
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add_interchange_test(
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name const_wire_arty
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part xc7a35tcsg324-1
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package csg324
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tcl run.tcl
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xdc wire.xdc
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sources wire.v
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)
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@ -1,6 +1,6 @@
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yosys -import
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read_verilog ff.v
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read_verilog $::env(SOURCES)
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synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
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@ -11,4 +11,4 @@ opt_clean
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setundef -zero -params
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write_json build/ff.json
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write_json $::env(OUT_JSON)
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17
fpga_interchange/examples/tests/counter/CMakeLists.txt
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17
fpga_interchange/examples/tests/counter/CMakeLists.txt
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@ -0,0 +1,17 @@
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add_interchange_test(
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name counter_basys3
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part xc7a35tcpg236-1
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package cpg236
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tcl run.tcl
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xdc counter.xdc
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sources counter.v
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)
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add_interchange_test(
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name counter_arty
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part xc7a35tcsg324-1
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package csg324
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tcl run.tcl
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xdc counter.xdc
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sources counter.v
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)
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@ -1,6 +1,6 @@
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yosys -import
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read_verilog counter.v
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read_verilog $::env(SOURCES)
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synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
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techmap -map ../remap.v
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@ -12,4 +12,4 @@ opt_clean
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setundef -zero -params
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write_json build/counter.json
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write_json $::env(OUT_JSON)
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17
fpga_interchange/examples/tests/ff/CMakeLists.txt
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17
fpga_interchange/examples/tests/ff/CMakeLists.txt
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add_interchange_test(
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name ff_basys3
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part xc7a35tcpg236-1
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package cpg236
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tcl run.tcl
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xdc ff.xdc
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sources ff.v
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)
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add_interchange_test(
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name ff_arty
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part xc7a35tcsg324-1
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package csg324
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tcl run.tcl
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xdc ff.xdc
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sources ff.v
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)
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@ -1,6 +1,6 @@
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yosys -import
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read_verilog wire.v
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read_verilog $::env(SOURCES)
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synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
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@ -11,4 +11,4 @@ opt_clean
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setundef -zero -params
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write_json build/wire.json
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write_json $::env(OUT_JSON)
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17
fpga_interchange/examples/tests/lut/CMakeLists.txt
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17
fpga_interchange/examples/tests/lut/CMakeLists.txt
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add_interchange_test(
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name lut_basys3
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part xc7a35tcpg236-1
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package cpg236
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tcl run.tcl
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xdc lut.xdc
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sources lut.v
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)
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add_interchange_test(
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name lut_arty
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part xc7a35tcsg324-1
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package csg324
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tcl run.tcl
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xdc lut.xdc
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sources lut.v
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)
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@ -1,6 +1,6 @@
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yosys -import
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read_verilog lut.v
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read_verilog $::env(SOURCES)
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synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
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@ -11,4 +11,4 @@ opt_clean
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setundef -zero -params
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write_json build/lut.json
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write_json $::env(OUT_JSON)
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17
fpga_interchange/examples/tests/wire/CMakeLists.txt
Normal file
17
fpga_interchange/examples/tests/wire/CMakeLists.txt
Normal file
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add_interchange_test(
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name wire_basys3
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part xc7a35tcpg236-1
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package cpg236
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tcl run.tcl
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xdc wire.xdc
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sources wire.v
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)
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add_interchange_test(
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name wire_arty
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part xc7a35tcsg324-1
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package csg324
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tcl run.tcl
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xdc wire.xdc
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sources wire.v
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)
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@ -1,6 +1,6 @@
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yosys -import
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read_verilog wire.v
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read_verilog $::env(SOURCES)
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synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
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@ -11,4 +11,4 @@ opt_clean
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setundef -zero -params
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write_json build/wire.json
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write_json $::env(OUT_JSON)
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@ -1,8 +0,0 @@
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DESIGN := wire
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DESIGN_TOP := top
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PACKAGE := csg324
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include ../template.mk
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build/wire.json: wire.v | build
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yosys -c run.tcl
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