fpga_interchange: tests: add cmake functions

Also move all tests in a tests directory

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

fpga_interchange/examples/const_wire/Makefile

@@ -1,8 +0,0 @@
-DESIGN := wire
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/wire.json: wire.v | build
-	yosys -c run.tcl

fpga_interchange/examples/counter/Makefile

@@ -1,8 +0,0 @@
-DESIGN := counter
-DESIGN_TOP := top
-PACKAGE := cpg236
-
-include ../template.mk
-
-build/counter.json: counter.v | build
-	yosys -c run.tcl

fpga_interchange/examples/ff/Makefile

@@ -1,8 +0,0 @@
-DESIGN := ff
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/ff.json: ff.v | build
-	yosys -c run.tcl

fpga_interchange/examples/lut/Makefile

@@ -1,8 +0,0 @@
-DESIGN := lut
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/lut.json: lut.v | build
-	yosys -c run.tcl

fpga_interchange/examples/tests.cmake

@@ -0,0 +1,115 @@
+function(add_interchange_test)
+    # ~~~
+    # add_interchange_test(
+    #    name <name>
+    #    part <part>
+    #    part <package>
+    #    tcl <tcl>
+    #    xdc <xdc>
+    #    top <top name>
+    #    sources <sources list>
+    # )
+    # ~~~
+
+    set(options)
+    set(oneValueArgs name part package tcl xdc top)
+    set(multiValueArgs sources)
+
+    cmake_parse_arguments(
+        add_interchange_test
+        "${options}"
+        "${oneValueArgs}"
+        "${multiValueArgs}"
+        ${ARGN}
+    )
+
+    set(name ${add_interchange_test_name})
+    set(part ${add_interchange_test_part})
+    set(package ${add_interchange_test_package})
+    set(top ${add_interchange_test_top})
+    set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
+    set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
+
+    set(sources)
+    foreach(source ${add_interchange_test_sources})
+        list(APPEND sources ${CMAKE_CURRENT_SOURCE_DIR}/${source})
+    endforeach()
+
+    if (NOT DEFINED top)
+        # Setting default top value
+        set(top "top")
+    endif()
+
+    # Synthesis
+    set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
+    add_custom_command(
+        OUTPUT ${synth_json}
+        COMMAND
+            SOURCES=${sources}
+            OUT_JSON=${synth_json}
+            yosys -c ${tcl}
+        DEPENDS ${sources}
+    )
+
+    add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json})
+
+    # Logical Netlist
+    set(device_target constraints-luts-${part}-device)
+    get_property(device_loc TARGET constraints-luts-${part}-device PROPERTY LOCATION)
+
+    set(netlist ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist)
+    add_custom_command(
+        OUTPUT ${netlist}
+        COMMAND
+            python3 -mfpga_interchange.yosys_json
+                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+                --device ${device_loc}
+                --top ${top}
+                ${synth_json}
+                ${netlist}
+        DEPENDS
+            ${synth_json}
+            ${device_target}
+    )
+
+    add_custom_target(test-${family}-${name}-netlist DEPENDS ${netlist})
+
+    set(chipdb_target chipdb-${part}-bba)
+
+    # Physical Netlist
+    set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys)
+    add_custom_command(
+        OUTPUT ${phys}
+        COMMAND
+            nextpnr-fpga_interchange
+                --chipdb ${chipdb_dir}/chipdb-${part}.bba
+                --xdc ${xdc}
+                --netlist ${netlist}
+                --phys ${phys}
+                --package ${package}
+        DEPENDS
+            ${netlist}
+            ${chipdb_target}
+    )
+
+    add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})
+
+    set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
+    add_custom_command(
+        OUTPUT ${dcp}
+        COMMAND
+            RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
+            ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh
+            com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
+            ${netlist} ${phys} ${xdc} ${dcp}
+        DEPENDS
+            ${phys}
+            ${netlist}
+    )
+
+    add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
+    add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
+endfunction()
+
+add_custom_target(all-${family}-tests)
+add_subdirectory(${family}/examples/tests)

fpga_interchange/examples/tests/CMakeLists.txt

@@ -0,0 +1,5 @@
+add_subdirectory(wire)
+add_subdirectory(const_wire)
+add_subdirectory(counter)
+add_subdirectory(ff)
+add_subdirectory(lut)

fpga_interchange/examples/tests/const_wire/CMakeLists.txt

@@ -0,0 +1,17 @@
+add_interchange_test(
+    name const_wire_basys3
+    part xc7a35tcpg236-1
+    package cpg236
+    tcl run.tcl
+    xdc wire.xdc
+    sources wire.v
+)
+
+add_interchange_test(
+    name const_wire_arty
+    part xc7a35tcsg324-1
+    package csg324
+    tcl run.tcl
+    xdc wire.xdc
+    sources wire.v
+)

fpga_interchange/examples/tests/const_wire/run.tcl

@@ -1,6 +1,6 @@
 yosys -import
 
-read_verilog ff.v
+read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
 
@@ -11,4 +11,4 @@ opt_clean
 
 setundef -zero -params
 
-write_json build/ff.json
+write_json $::env(OUT_JSON)

fpga_interchange/examples/tests/counter/CMakeLists.txt

@@ -0,0 +1,17 @@
+add_interchange_test(
+    name counter_basys3
+    part xc7a35tcpg236-1
+    package cpg236
+    tcl run.tcl
+    xdc counter.xdc
+    sources counter.v
+)
+
+add_interchange_test(
+    name counter_arty
+    part xc7a35tcsg324-1
+    package csg324
+    tcl run.tcl
+    xdc counter.xdc
+    sources counter.v
+)

fpga_interchange/examples/tests/counter/run.tcl

@@ -1,6 +1,6 @@
 yosys -import
 
-read_verilog counter.v
+read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
 techmap -map ../remap.v
@@ -12,4 +12,4 @@ opt_clean
 
 setundef -zero -params
 
-write_json build/counter.json
+write_json $::env(OUT_JSON)

fpga_interchange/examples/tests/ff/CMakeLists.txt

@@ -0,0 +1,17 @@
+add_interchange_test(
+    name ff_basys3
+    part xc7a35tcpg236-1
+    package cpg236
+    tcl run.tcl
+    xdc ff.xdc
+    sources ff.v
+)
+
+add_interchange_test(
+    name ff_arty
+    part xc7a35tcsg324-1
+    package csg324
+    tcl run.tcl
+    xdc ff.xdc
+    sources ff.v
+)

fpga_interchange/examples/tests/ff/run.tcl

@@ -1,6 +1,6 @@
 yosys -import
 
-read_verilog wire.v
+read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
 
@@ -11,4 +11,4 @@ opt_clean
 
 setundef -zero -params
 
-write_json build/wire.json
+write_json $::env(OUT_JSON)

fpga_interchange/examples/tests/lut/CMakeLists.txt

@@ -0,0 +1,17 @@
+add_interchange_test(
+    name lut_basys3
+    part xc7a35tcpg236-1
+    package cpg236
+    tcl run.tcl
+    xdc lut.xdc
+    sources lut.v
+)
+
+add_interchange_test(
+    name lut_arty
+    part xc7a35tcsg324-1
+    package csg324
+    tcl run.tcl
+    xdc lut.xdc
+    sources lut.v
+)

fpga_interchange/examples/tests/lut/run.tcl

@@ -1,6 +1,6 @@
 yosys -import
 
-read_verilog lut.v
+read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
 
@@ -11,4 +11,4 @@ opt_clean
 
 setundef -zero -params
 
-write_json build/lut.json
+write_json $::env(OUT_JSON)

fpga_interchange/examples/tests/wire/CMakeLists.txt

@@ -0,0 +1,17 @@
+add_interchange_test(
+    name wire_basys3
+    part xc7a35tcpg236-1
+    package cpg236
+    tcl run.tcl
+    xdc wire.xdc
+    sources wire.v
+)
+
+add_interchange_test(
+    name wire_arty
+    part xc7a35tcsg324-1
+    package csg324
+    tcl run.tcl
+    xdc wire.xdc
+    sources wire.v
+)

fpga_interchange/examples/tests/wire/run.tcl

@@ -1,6 +1,6 @@
 yosys -import
 
-read_verilog wire.v
+read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
 
@@ -11,4 +11,4 @@ opt_clean
 
 setundef -zero -params
 
-write_json build/wire.json
+write_json $::env(OUT_JSON)

fpga_interchange/examples/wire/Makefile

@@ -1,8 +0,0 @@
-DESIGN := wire
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/wire.json: wire.v | build
-	yosys -c run.tcl