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mistral: preliminary bitstream info

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This commit is contained in:
Lofty 2021-12-22 12:01:24 +00:00
parent 34b7cdb533
commit 78474a5dec
1 changed files with 41 additions and 0 deletions
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41
mistral/bitstream.cc
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@ -118,6 +118,45 @@ struct MistralBitgen
cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
}
void write_m10k_cell(CellInfo* ci, int x, int y, int bi)
{
auto pos = CycloneV::xy2pos(x, y);
// Notes:
// DATA_FLOW_THRU is probably transparent reads.
cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SAEN_DELAY, bi, 2);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WL_DELAY, bi, 2);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SAEN_DELAY, bi, 2);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WL_DELAY, bi, 2);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WR_TIMER_PULSE, bi, 0x0b);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 1);
cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0);
for (int bi = 0; bi < 256; bi++)
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff);
}
void write_cells()
{
for (auto &cell : ctx->cells) {
@ -128,6 +167,8 @@ struct MistralBitgen
write_io_cell(ci, loc.x, loc.y, bi);
else if (ctx->is_clkbuf_cell(ci->type))
write_clkbuf_cell(ci, loc.x, loc.y, bi);
else if (ci->type == id_MISTRAL_M10K)
write_m10k_cell(ci, loc.x, loc.y, bi);
}
}