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timing: Model clock to Q times

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-24 11:46:14 +02:00
parent 4359197dfe
commit 7858663aa7
2 changed files with 18 additions and 0 deletions
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3
common/timing.cc
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@ -88,6 +88,9 @@ void assign_budget(Context *ctx)
IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
if (clock_domain != IdString()) {
delay_t slack = delay_t(1.0e12 / ctx->target_freq); // TODO: clock constraints
delay_t clkToQ;
if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ))
slack -= clkToQ;
if (port.second.net)
follow_net(ctx, port.second.net, 0, slack);
}

15
ice40/arch.cc
View File

@ -733,6 +733,14 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
} else if (fromPort == id("I2") && toPort == id("COUT")) {
delay = 230;
return true;
} else if (fromPort == id("CLK") && toPort == id("O")) {
delay = 540;
return true;
}
} else if (cell->type == id("ICESTORM_RAM")) {
if (fromPort == id("RCLK")) {
delay = 2140;
return true;
}
}
return false;
@ -743,6 +751,11 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
if (port != id("LO") && port != id("CIN") && port != id("COUT"))
return id("CLK");
} else if (cell->type == id("ICESTORM_RAM")) {
if (port.str(this)[0] == 'R')
return id("RCLK");
else
return id("WCLK");
}
return IdString();
}
@ -751,6 +764,8 @@ bool Arch::isClockPort(const CellInfo *cell, IdString port) const
{
if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
return true;
if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK"))))
return true;
return false;
}