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Route dfr clock properly

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This commit is contained in:
Miodrag Milanovic 2024-07-03 10:41:12 +02:00
parent d1207b10c0
commit 7869140621
4 changed files with 29 additions and 8 deletions
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14
himbaechel/uarch/ng-ultra/gen/arch_gen.py
View File

@ -660,6 +660,20 @@ def main():
tmp = name.replace("TILE[","").replace("CGB[","").replace("]","")
x,y = tmp.split("x")
lobe = ((int(y)-1) // 12)*2 + (1 if int(x)>46 else 0) + 1
elif item["orig"].startswith("IOB") or item["orig"].startswith("HSSL"):
match item["orig"]:
case "IOB0" | "IOB1":
lobe = 5
case "IOB6" | "IOB7":
lobe = 6
case "IOB8" | "IOB9" | "IOB10":
lobe = 2
case "IOB11" | "IOB12" | "IOB13":
lobe = 1
case "IOB2" | "IOB3" | "HSSL0" | "HSSL1" | "HSSL2" | "HSSL3":
lobe = 7
case "IOB4" | "IOB5" | "HSSL4" | "HSSL5" | "HSSL6" | "HSSL7":
lobe = 8
ti.extra_data = TileExtraData(ch.strs.id(name),lobe)
for name, data in tilegrid.items():

11
himbaechel/uarch/ng-ultra/ng_ultra.cc
View File

@ -154,9 +154,9 @@ void NgUltraImpl::init(Context *ctx)
ring_clock_sinks[id_WFG].insert(id_ZI);
// IOB
// ring_clock_sinks[id_DFR].insert(id_CK);
// ring_clock_sinks[id_DDFR].insert(id_CK);
// ring_clock_sinks[id_DDFR].insert(id_CKF);
ring_over_tile_clock_sinks[id_DFR].insert(id_CK);
ring_over_tile_clock_sinks[id_DDFR].insert(id_CK);
ring_over_tile_clock_sinks[id_DDFR].insert(id_CKF);
// ring_clock_sinks[id_IOM].insert(id_ALCK1);
// ring_clock_sinks[id_IOM].insert(id_ALCK2);
// ring_clock_sinks[id_IOM].insert(id_ALCK3);
@ -217,6 +217,11 @@ bool NgUltraImpl::is_ring_clock_sink(const PortRef &ref)
return ring_clock_sinks.count(ref.cell->type) && ring_clock_sinks[ref.cell->type].count(ref.port);
}
bool NgUltraImpl::is_ring_over_tile_clock_sink(const PortRef &ref)
{
return ring_over_tile_clock_sinks.count(ref.cell->type) && ring_over_tile_clock_sinks[ref.cell->type].count(ref.port);
}
bool NgUltraImpl::is_tube_clock_sink(const PortRef &ref)
{
return tube_clock_sinks.count(ref.cell->type) && tube_clock_sinks[ref.cell->type].count(ref.port);

2
himbaechel/uarch/ng-ultra/ng_ultra.h
View File

@ -70,6 +70,7 @@ public:
bool is_fabric_clock_sink(const PortRef &ref);
bool is_ring_clock_sink(const PortRef &ref);
bool is_ring_over_tile_clock_sink(const PortRef &ref);
bool is_tube_clock_sink(const PortRef &ref);
bool is_ring_clock_source(const PortRef &ref);
@ -101,6 +102,7 @@ private:
dict<IdString,pool<IdString>> fabric_clock_sinks;
dict<IdString,pool<IdString>> ring_clock_sinks;
dict<IdString,pool<IdString>> ring_over_tile_clock_sinks;
dict<IdString,pool<IdString>> tube_clock_sinks;
dict<IdString,pool<IdString>> ring_clock_source;

10
himbaechel/uarch/ng-ultra/pack.cc
View File

@ -1361,7 +1361,7 @@ void NgUltraPacker::insert_ioms()
if (uarch->global_capable_bels.count(bel)==0)
continue;
for (const auto &usr : ni->users) {
if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_clock_sink(usr) || uarch->is_tube_clock_sink(usr)) {
if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_clock_sink(usr) || uarch->is_tube_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
pins_needing_iom.emplace_back(ni->name);
break;
}
@ -1504,7 +1504,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port)
bool in_fabric = false;
bool in_ring = false;
for (const auto &usr : net->users) {
if (uarch->is_fabric_clock_sink(usr) || uarch->is_tube_clock_sink(usr))
if (uarch->is_fabric_clock_sink(usr) || uarch->is_tube_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr))
in_fabric = true;
else
in_ring = true;
@ -1519,7 +1519,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port)
NetInfo *net_zo = ctx->createNet(ctx->id(net->name.str(ctx) + "$ZO"));
wfb->connectPort(id_ZO, net_zo);
for (const auto &usr : net->users) {
if (uarch->is_fabric_clock_sink(usr)) {
if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
usr.cell->disconnectPort(usr.port);
usr.cell->connectPort(usr.port, net_zo);
}
@ -2083,7 +2083,7 @@ void NgUltraPacker::duplicate_gck()
log_info(" Lowskew signal '%s'\n", glb_net->name.c_str(ctx));
dict<int, std::vector<PortRef>> connections;
for (const auto &usr : glb_net->users) {
if (uarch->is_fabric_clock_sink(usr)) {
if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
if (usr.cell->bel==BelId()) {
log_error("Cell '%s' not placed\n",usr.cell->name.c_str(ctx));
}
@ -2144,7 +2144,7 @@ void NgUltraPacker::insert_bypass_gck()
log_info(" Lowskew signal '%s'\n", glb_net->name.c_str(ctx));
dict<int, std::vector<PortRef>> connections;
for (const auto &usr : glb_net->users) {
if (uarch->is_fabric_clock_sink(usr)) {
if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
if (usr.cell->bel==BelId()) {
log_error("Cell '%s' not placed\n",usr.cell->name.c_str(ctx));
}