From 78691406210ab8c46966fe2822d3f0fb4a188e61 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 3 Jul 2024 10:41:12 +0200 Subject: [PATCH] Route dfr clock properly --- himbaechel/uarch/ng-ultra/gen/arch_gen.py | 14 ++++++++++++++ himbaechel/uarch/ng-ultra/ng_ultra.cc | 11 ++++++++--- himbaechel/uarch/ng-ultra/ng_ultra.h | 2 ++ himbaechel/uarch/ng-ultra/pack.cc | 10 +++++----- 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/himbaechel/uarch/ng-ultra/gen/arch_gen.py b/himbaechel/uarch/ng-ultra/gen/arch_gen.py index 3cfb5191..a63dfabf 100644 --- a/himbaechel/uarch/ng-ultra/gen/arch_gen.py +++ b/himbaechel/uarch/ng-ultra/gen/arch_gen.py @@ -660,6 +660,20 @@ def main(): tmp = name.replace("TILE[","").replace("CGB[","").replace("]","") x,y = tmp.split("x") lobe = ((int(y)-1) // 12)*2 + (1 if int(x)>46 else 0) + 1 + elif item["orig"].startswith("IOB") or item["orig"].startswith("HSSL"): + match item["orig"]: + case "IOB0" | "IOB1": + lobe = 5 + case "IOB6" | "IOB7": + lobe = 6 + case "IOB8" | "IOB9" | "IOB10": + lobe = 2 + case "IOB11" | "IOB12" | "IOB13": + lobe = 1 + case "IOB2" | "IOB3" | "HSSL0" | "HSSL1" | "HSSL2" | "HSSL3": + lobe = 7 + case "IOB4" | "IOB5" | "HSSL4" | "HSSL5" | "HSSL6" | "HSSL7": + lobe = 8 ti.extra_data = TileExtraData(ch.strs.id(name),lobe) for name, data in tilegrid.items(): diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.cc b/himbaechel/uarch/ng-ultra/ng_ultra.cc index 92b675db..656f1ccd 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.cc +++ b/himbaechel/uarch/ng-ultra/ng_ultra.cc @@ -154,9 +154,9 @@ void NgUltraImpl::init(Context *ctx) ring_clock_sinks[id_WFG].insert(id_ZI); // IOB - // ring_clock_sinks[id_DFR].insert(id_CK); - // ring_clock_sinks[id_DDFR].insert(id_CK); - // ring_clock_sinks[id_DDFR].insert(id_CKF); + ring_over_tile_clock_sinks[id_DFR].insert(id_CK); + ring_over_tile_clock_sinks[id_DDFR].insert(id_CK); + ring_over_tile_clock_sinks[id_DDFR].insert(id_CKF); // ring_clock_sinks[id_IOM].insert(id_ALCK1); // ring_clock_sinks[id_IOM].insert(id_ALCK2); // ring_clock_sinks[id_IOM].insert(id_ALCK3); @@ -217,6 +217,11 @@ bool NgUltraImpl::is_ring_clock_sink(const PortRef &ref) return ring_clock_sinks.count(ref.cell->type) && ring_clock_sinks[ref.cell->type].count(ref.port); } +bool NgUltraImpl::is_ring_over_tile_clock_sink(const PortRef &ref) +{ + return ring_over_tile_clock_sinks.count(ref.cell->type) && ring_over_tile_clock_sinks[ref.cell->type].count(ref.port); +} + bool NgUltraImpl::is_tube_clock_sink(const PortRef &ref) { return tube_clock_sinks.count(ref.cell->type) && tube_clock_sinks[ref.cell->type].count(ref.port); diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.h b/himbaechel/uarch/ng-ultra/ng_ultra.h index 0d6e780e..8aac92c9 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.h +++ b/himbaechel/uarch/ng-ultra/ng_ultra.h @@ -70,6 +70,7 @@ public: bool is_fabric_clock_sink(const PortRef &ref); bool is_ring_clock_sink(const PortRef &ref); + bool is_ring_over_tile_clock_sink(const PortRef &ref); bool is_tube_clock_sink(const PortRef &ref); bool is_ring_clock_source(const PortRef &ref); @@ -101,6 +102,7 @@ private: dict> fabric_clock_sinks; dict> ring_clock_sinks; + dict> ring_over_tile_clock_sinks; dict> tube_clock_sinks; dict> ring_clock_source; diff --git a/himbaechel/uarch/ng-ultra/pack.cc b/himbaechel/uarch/ng-ultra/pack.cc index 1907d66a..d0083120 100644 --- a/himbaechel/uarch/ng-ultra/pack.cc +++ b/himbaechel/uarch/ng-ultra/pack.cc @@ -1361,7 +1361,7 @@ void NgUltraPacker::insert_ioms() if (uarch->global_capable_bels.count(bel)==0) continue; for (const auto &usr : ni->users) { - if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_clock_sink(usr) || uarch->is_tube_clock_sink(usr)) { + if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_clock_sink(usr) || uarch->is_tube_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) { pins_needing_iom.emplace_back(ni->name); break; } @@ -1504,7 +1504,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port) bool in_fabric = false; bool in_ring = false; for (const auto &usr : net->users) { - if (uarch->is_fabric_clock_sink(usr) || uarch->is_tube_clock_sink(usr)) + if (uarch->is_fabric_clock_sink(usr) || uarch->is_tube_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) in_fabric = true; else in_ring = true; @@ -1519,7 +1519,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port) NetInfo *net_zo = ctx->createNet(ctx->id(net->name.str(ctx) + "$ZO")); wfb->connectPort(id_ZO, net_zo); for (const auto &usr : net->users) { - if (uarch->is_fabric_clock_sink(usr)) { + if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) { usr.cell->disconnectPort(usr.port); usr.cell->connectPort(usr.port, net_zo); } @@ -2083,7 +2083,7 @@ void NgUltraPacker::duplicate_gck() log_info(" Lowskew signal '%s'\n", glb_net->name.c_str(ctx)); dict> connections; for (const auto &usr : glb_net->users) { - if (uarch->is_fabric_clock_sink(usr)) { + if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) { if (usr.cell->bel==BelId()) { log_error("Cell '%s' not placed\n",usr.cell->name.c_str(ctx)); } @@ -2144,7 +2144,7 @@ void NgUltraPacker::insert_bypass_gck() log_info(" Lowskew signal '%s'\n", glb_net->name.c_str(ctx)); dict> connections; for (const auto &usr : glb_net->users) { - if (uarch->is_fabric_clock_sink(usr)) { + if (uarch->is_fabric_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) { if (usr.cell->bel==BelId()) { log_error("Cell '%s' not placed\n",usr.cell->name.c_str(ctx)); }