machxo2: Remove pybindings unneeded files from examples and update README.md and scripts accordingly. Delete resources directory.
This commit is contained in:
William D. Jones
gatecat
parent
539651609c
commit
78880e1fdf
@ -1,241 +0,0 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NO_PYTHON
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#include "arch_pybindings.h"
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#include "nextpnr.h"
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#include "pybindings.h"
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#include "pywrappers.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace PythonConversion {
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template <> struct string_converter<const IdString &>
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{
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const IdString &from_str(Context *ctx, std::string name) { NPNR_ASSERT_FALSE("unsupported"); }
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std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); }
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};
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} // namespace PythonConversion
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void arch_wrap_python()
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{
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using namespace PythonConversion;
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auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>());
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auto dxy_cls = class_<ContextualWrapper<DecalXY>>("DecalXY_", no_init);
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readwrite_wrapper<DecalXY, decltype(&DecalXY::decal), &DecalXY::decal, conv_to_str<DecalId>,
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conv_from_str<DecalId>>::def_wrap(dxy_cls, "decal");
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readwrite_wrapper<DecalXY, decltype(&DecalXY::x), &DecalXY::x, pass_through<float>, pass_through<float>>::def_wrap(
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dxy_cls, "x");
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readwrite_wrapper<DecalXY, decltype(&DecalXY::y), &DecalXY::y, pass_through<float>, pass_through<float>>::def_wrap(
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dxy_cls, "y");
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auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init)
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.def("checksum", &Context::checksum)
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.def("pack", &Context::pack)
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.def("place", &Context::place)
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.def("route", &Context::route);
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class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
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class_<DelayInfo>("DelayInfo").def("maxDelay", &DelayInfo::maxDelay).def("minDelay", &DelayInfo::minDelay);
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fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>,
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conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
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fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
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conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
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fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
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conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
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fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
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addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
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fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
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ctx_cls, "unbindBel");
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fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>,
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conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
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fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
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deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
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fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels,
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wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels");
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fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
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conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
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fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins,
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wrap_context<const std::vector<BelPin> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
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"getWireBelPins");
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fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
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conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
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fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
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addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
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fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
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ctx_cls, "unbindWire");
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fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
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conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
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fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>,
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conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
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fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
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deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
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fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires,
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wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires");
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fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips,
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wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips");
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fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
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conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
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fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
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addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
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fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
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ctx_cls, "unbindPip");
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fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
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conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
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fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>,
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conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
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fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
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deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
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fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill,
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wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
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"getPipsDownhill");
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fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill,
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wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
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fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases,
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wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases");
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fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
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conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
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fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>,
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conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire");
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fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>,
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conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay");
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fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<DelayInfo>,
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pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
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fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap(
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ctx_cls, "getChipName");
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fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls,
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"archId");
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fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>,
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conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY");
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typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
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typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
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typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
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readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
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"cells");
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readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
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"nets");
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fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
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pass_through<float>>::def_wrap(ctx_cls, "addClock");
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// Generic arch construction API
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fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdString>,
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conv_from_str<IdString>, pass_through<int>, pass_through<int>>::def_wrap(ctx_cls, "addWire",
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(arg("name"), "type", "x",
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"y"));
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fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdString>,
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conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
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pass_through<Loc>>::def_wrap(ctx_cls, "addPip",
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(arg("name"), "type", "srcWire", "dstWire", "delay", "loc"));
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fn_wrapper_5a_v<Context, decltype(&Context::addAlias), &Context::addAlias, conv_from_str<IdString>,
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conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
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pass_through<DelayInfo>>::def_wrap(ctx_cls, "addAlias",
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(arg("name"), "type", "srcWire", "dstWire", "delay"));
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fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>,
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conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
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(arg("name"), "type",
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"loc", "gb"));
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fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdString>,
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conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput",
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(arg("bel"), "name", "wire"));
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fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdString>,
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conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput",
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(arg("bel"), "name", "wire"));
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fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdString>,
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conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout",
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(arg("bel"), "name", "wire"));
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fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdString>,
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conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupBel", (arg("group"), "bel"));
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fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdString>,
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conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupWire", (arg("group"), "wire"));
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fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdString>,
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conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupPip", (arg("group"), "pip"));
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fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdString>,
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conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupGroup", (arg("group"), "grp"));
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fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
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pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (arg("decal"), "graphic"));
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fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<DecalId>,
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unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", (arg("wire"), "decalxy"));
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fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<DecalId>,
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unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", (arg("pip"), "decalxy"));
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fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<DecalId>,
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unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", (arg("bel"), "decalxy"));
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fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>,
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unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", (arg("group"), "decalxy"));
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fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
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conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr",
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(arg("wire"), "key", "value"));
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fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
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conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr",
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(arg("bel"), "key", "value"));
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fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
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conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr",
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(arg("pip"), "key", "value"));
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fn_wrapper_1a_v<Context, decltype(&Context::setLutK), &Context::setLutK, pass_through<int>>::def_wrap(
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ctx_cls, "setLutK", arg("K"));
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fn_wrapper_2a_v<Context, decltype(&Context::setDelayScaling), &Context::setDelayScaling, pass_through<double>,
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pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", (arg("scale"), "offset"));
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fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock,
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conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock",
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(arg("cell"), "port"));
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fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay,
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conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
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pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay",
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(arg("cell"), "fromPort", "toPort", "delay"));
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fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold,
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conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
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pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold",
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(arg("cell"), "port", "clock", "setup", "hold"));
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fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut,
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conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
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pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut",
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(arg("cell"), "port", "clock", "clktoq"));
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WRAP_MAP_UPTR(CellMap, "IdCellMap");
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WRAP_MAP_UPTR(NetMap, "IdNetMap");
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WRAP_MAP(HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
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WRAP_VECTOR(const std::vector<IdString>, conv_to_str<IdString>);
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}
|
|
||||||
|
|
||||||
NEXTPNR_NAMESPACE_END
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,31 +0,0 @@
|
|||||||
/*
|
|
||||||
* nextpnr -- Next Generation Place and Route
|
|
||||||
*
|
|
||||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
|
||||||
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
|
|
||||||
*
|
|
||||||
* Permission to use, copy, modify, and/or distribute this software for any
|
|
||||||
* purpose with or without fee is hereby granted, provided that the above
|
|
||||||
* copyright notice and this permission notice appear in all copies.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#ifndef ARCH_PYBINDINGS_H
|
|
||||||
#define ARCH_PYBINDINGS_H
|
|
||||||
#ifndef NO_PYTHON
|
|
||||||
|
|
||||||
#include "nextpnr.h"
|
|
||||||
#include "pybindings.h"
|
|
||||||
|
|
||||||
NEXTPNR_NAMESPACE_BEGIN
|
|
||||||
|
|
||||||
NEXTPNR_NAMESPACE_END
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
4
machxo2/examples/.gitignore
vendored
4
machxo2/examples/.gitignore
vendored
@ -1,6 +1,4 @@
|
|||||||
blinky.fasm
|
|
||||||
__pycache__
|
|
||||||
*.pyc
|
|
||||||
pnrblinky.v
|
pnrblinky.v
|
||||||
/blinky_simtest
|
/blinky_simtest
|
||||||
*.vcd
|
*.vcd
|
||||||
|
abc.history
|
||||||
|
|||||||
@ -1,15 +1,16 @@
|
|||||||
# MachXO2 Architecture Example
|
# MachXO2 Architecture Example
|
||||||
|
|
||||||
This contains a simple example of the nextpnr machxo2 API. As time goes on,
|
This contains a simple example of running `nextpnr-machxo2`:
|
||||||
python scripts required as boilerplate will be removed.
|
|
||||||
|
|
||||||
- simple.py procedurally generates a simple FPGA architecture with IO at the edges,
|
* `simple.sh` generates JSON output (`pnrblinky.json`) of a classic blinky
|
||||||
logic slices in all other tiles, and interconnect only between adjacent tiles
|
example from `blinky.v`.
|
||||||
|
* `simtest.sh` will use `yosys` to generate a Verilog file from
|
||||||
|
`pnrblinky.json`, called `pnrblinky.v`. It will then and compare
|
||||||
|
`pnrblinky.v`'s simulation behavior to the original verilog file (`blinky.v`)
|
||||||
|
using the [`iverilog`](http://iverilog.icarus.com) compiler and `vvp`
|
||||||
|
runtime. This is known as post-place-and-route simulation.
|
||||||
|
|
||||||
- simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)
|
As `nextpnr-machxo2` is developed the `nextpnr` invocation in `simple.sh` and
|
||||||
|
`simtest.sh` is subject to change. Other command invocations, such as `yosys`,
|
||||||
- write_fasm.py uses the nextpnr Python API to write a FASM file for a design
|
_should_ remain unchanged, even as files under the [synth](../synth) directory
|
||||||
|
change.
|
||||||
- bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design
|
|
||||||
|
|
||||||
- Run simple.sh to build an example design on the FPGA above
|
|
||||||
|
|||||||
@ -1,17 +0,0 @@
|
|||||||
from write_fasm import *
|
|
||||||
from simple_config import K
|
|
||||||
|
|
||||||
# Need to tell FASM generator how to write parameters
|
|
||||||
# (celltype, parameter) -> ParameterConfig
|
|
||||||
param_map = {
|
|
||||||
("GENERIC_SLICE", "K"): ParameterConfig(write=False),
|
|
||||||
("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
|
|
||||||
("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
|
||||||
|
|
||||||
("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
|
||||||
("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
|
||||||
("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
|
||||||
}
|
|
||||||
|
|
||||||
with open("blinky.fasm", "w") as f:
|
|
||||||
write_fasm(ctx, param_map, f)
|
|
||||||
@ -1,77 +0,0 @@
|
|||||||
from simple_config import *
|
|
||||||
|
|
||||||
def is_io(x, y):
|
|
||||||
return x == 0 or x == X-1 or y == 0 or y == Y-1
|
|
||||||
|
|
||||||
for x in range(X):
|
|
||||||
for y in range(Y):
|
|
||||||
# Bel port wires
|
|
||||||
for z in range(N):
|
|
||||||
ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y)
|
|
||||||
ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y)
|
|
||||||
ctx.addWire(name="X%dY%dZ%d_F" % (x, y, z), type="BEL_F", x=x, y=y)
|
|
||||||
for i in range(K):
|
|
||||||
ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y)
|
|
||||||
# Local wires
|
|
||||||
for l in range(Wl):
|
|
||||||
ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y)
|
|
||||||
# Create bels
|
|
||||||
if is_io(x, y):
|
|
||||||
if x == y:
|
|
||||||
continue
|
|
||||||
for z in range(2):
|
|
||||||
ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
|
|
||||||
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
|
|
||||||
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
|
|
||||||
ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
|
|
||||||
else:
|
|
||||||
for z in range(N):
|
|
||||||
ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
|
|
||||||
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
|
|
||||||
for k in range(K):
|
|
||||||
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))
|
|
||||||
ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="F", wire="X%dY%dZ%d_F" % (x, y, z))
|
|
||||||
ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z))
|
|
||||||
|
|
||||||
for x in range(X):
|
|
||||||
for y in range(Y):
|
|
||||||
# Pips driving bel input wires
|
|
||||||
# Bel input wires are driven by every Si'th local with an offset
|
|
||||||
def create_input_pips(dst, offset, skip):
|
|
||||||
for i in range(offset % skip, Wl, skip):
|
|
||||||
src = "X%dY%d_LOCAL%d" % (x, y, i)
|
|
||||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT",
|
|
||||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
|
||||||
for z in range(N):
|
|
||||||
create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si)
|
|
||||||
for k in range(K):
|
|
||||||
create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si)
|
|
||||||
|
|
||||||
# Pips from bel outputs to locals
|
|
||||||
def create_output_pips(dst, offset, skip):
|
|
||||||
for i in range(offset % skip, N, skip):
|
|
||||||
src = "X%dY%dZ%d_F" % (x, y, i)
|
|
||||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
|
|
||||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
|
||||||
src = "X%dY%dZ%d_Q" % (x, y, i)
|
|
||||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
|
|
||||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
|
||||||
# Pips from neighbour locals to locals
|
|
||||||
def create_neighbour_pips(dst, nx, ny, offset, skip):
|
|
||||||
if nx < 0 or nx >= X or ny < 0 or ny >= Y:
|
|
||||||
return
|
|
||||||
for i in range(offset % skip, Wl, skip):
|
|
||||||
src = "X%dY%d_LOCAL%d" % (nx, ny, i)
|
|
||||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR",
|
|
||||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
|
||||||
for l in range(Wl):
|
|
||||||
dst = "X%dY%d_LOCAL%d" % (x, y, l)
|
|
||||||
create_output_pips(dst, l % Sq, Sq)
|
|
||||||
create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x-1, y, (l + 2) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x-1, y+1, (l + 2) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x, y-1, (l + 3) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl)
|
|
||||||
create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
|
|
||||||
@ -1,5 +1,5 @@
|
|||||||
#!/usr/bin/env bash
|
#!/usr/bin/env bash
|
||||||
set -ex
|
set -ex
|
||||||
yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
|
yosys -p "tcl ../synth/synth_machxo2.tcl 4 blinky.json" blinky.v
|
||||||
${NEXTPNR:-../../nextpnr-machxo2} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
|
${NEXTPNR:-../../nextpnr-machxo2} --json blinky.json --write pnrblinky.json
|
||||||
yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
|
yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
|
||||||
|
|||||||
@ -1,15 +0,0 @@
|
|||||||
# Grid size including IOBs at edges
|
|
||||||
X = 12
|
|
||||||
Y = 12
|
|
||||||
# SLICEs per tile
|
|
||||||
N = 8
|
|
||||||
# LUT input count
|
|
||||||
K = 4
|
|
||||||
# Number of local wires
|
|
||||||
Wl = N*(K+1) + 8
|
|
||||||
# 1/Fc for bel input wire pips
|
|
||||||
Si = 4
|
|
||||||
# 1/Fc for Q to local wire pips
|
|
||||||
Sq = 4
|
|
||||||
# ~1/Fc local to neighbour local wire pips
|
|
||||||
Sl = 8
|
|
||||||
@ -1,13 +0,0 @@
|
|||||||
for cname, cell in ctx.cells:
|
|
||||||
if cell.type != "GENERIC_SLICE":
|
|
||||||
continue
|
|
||||||
if cname in ("$PACKER_GND", "$PACKER_VCC"):
|
|
||||||
continue
|
|
||||||
K = int(cell.params["K"])
|
|
||||||
ctx.addCellTimingClock(cell=cname, port="CLK")
|
|
||||||
for i in range(K):
|
|
||||||
ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
|
|
||||||
setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0))
|
|
||||||
ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2))
|
|
||||||
for i in range(K):
|
|
||||||
ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2))
|
|
||||||
@ -1,7 +1,7 @@
|
|||||||
#!/usr/bin/env bash
|
#!/usr/bin/env bash
|
||||||
set -ex
|
set -ex
|
||||||
yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
|
yosys -p "tcl ../synth/synth_machxo2.tcl 4 blinky.json" blinky.v
|
||||||
${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
|
${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --json blinky.json --write pnrblinky.json
|
||||||
yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
|
yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
|
||||||
iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
|
iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
|
||||||
vvp -N ./blinky_simtest
|
vvp -N ./blinky_simtest
|
||||||
|
|||||||
@ -1,51 +0,0 @@
|
|||||||
from collections import namedtuple
|
|
||||||
|
|
||||||
"""
|
|
||||||
write: set to True to enable writing this parameter to FASM
|
|
||||||
|
|
||||||
numeric: set to True to write this parameter as a bit array (width>1) or
|
|
||||||
single bit (width==1) named after the parameter. Otherwise this
|
|
||||||
parameter will be written as `name.value`
|
|
||||||
|
|
||||||
width: width of numeric parameter (ignored for non-numeric parameters)
|
|
||||||
|
|
||||||
alias: an alternative name for this parameter (parameter name used if alias
|
|
||||||
is None)
|
|
||||||
"""
|
|
||||||
ParameterConfig = namedtuple('ParameterConfig', 'write numeric width alias')
|
|
||||||
|
|
||||||
# FIXME use defaults= once Python 3.7 is standard
|
|
||||||
ParameterConfig.__new__.__defaults__ = (False, True, 1, None)
|
|
||||||
|
|
||||||
|
|
||||||
"""
|
|
||||||
Write a design as FASM
|
|
||||||
|
|
||||||
ctx: nextpnr context
|
|
||||||
paramCfg: map from (celltype, parametername) -> ParameterConfig describing how to write parameters
|
|
||||||
f: output file
|
|
||||||
"""
|
|
||||||
def write_fasm(ctx, paramCfg, f):
|
|
||||||
for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)):
|
|
||||||
print("# Net %s" % nname, file=f)
|
|
||||||
for wire, pip in sorted(net.wires, key=lambda x: str(x[1])):
|
|
||||||
if pip.pip != "":
|
|
||||||
print("%s" % pip.pip, file=f)
|
|
||||||
print("", file=f)
|
|
||||||
for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)):
|
|
||||||
print("# Cell %s at %s" % (cname, cell.bel), file=f)
|
|
||||||
for param, val in sorted(cell.params, key=lambda x: str(x)):
|
|
||||||
cfg = paramCfg[(cell.type, param)]
|
|
||||||
if not cfg.write:
|
|
||||||
continue
|
|
||||||
fasm_name = cfg.alias if cfg.alias is not None else param
|
|
||||||
if cfg.numeric:
|
|
||||||
if cfg.width == 1:
|
|
||||||
if int(val) != 0:
|
|
||||||
print("%s.%s" % (cell.bel, fasm_name), file=f)
|
|
||||||
else:
|
|
||||||
# Parameters with width >32 are direct binary, otherwise denary
|
|
||||||
print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, val), file=f)
|
|
||||||
else:
|
|
||||||
print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f)
|
|
||||||
print("", file=f)
|
|
||||||
@ -1,3 +0,0 @@
|
|||||||
#include "resource.h"
|
|
||||||
|
|
||||||
IDR_CHIPDB_1200 BINARYFILE "machxo2/chipdb/chipdb-1200.bin"
|
|
||||||
@ -1,24 +0,0 @@
|
|||||||
#include <cstdio>
|
|
||||||
#include <windows.h>
|
|
||||||
#include "nextpnr.h"
|
|
||||||
#include "resource.h"
|
|
||||||
|
|
||||||
NEXTPNR_NAMESPACE_BEGIN
|
|
||||||
|
|
||||||
const char *chipdb_blob_1200;
|
|
||||||
|
|
||||||
const char *LoadFileInResource(int name, int type, DWORD &size)
|
|
||||||
{
|
|
||||||
HMODULE handle = ::GetModuleHandle(NULL);
|
|
||||||
HRSRC rc = ::FindResource(handle, MAKEINTRESOURCE(name), MAKEINTRESOURCE(type));
|
|
||||||
HGLOBAL rcData = ::LoadResource(handle, rc);
|
|
||||||
size = ::SizeofResource(handle, rc);
|
|
||||||
return static_cast<const char *>(::LockResource(rcData));
|
|
||||||
}
|
|
||||||
void load_chipdb()
|
|
||||||
{
|
|
||||||
DWORD size = 0;
|
|
||||||
chipdb_blob_1200 = LoadFileInResource(IDR_CHIPDB_1200, BINARYFILE, size);
|
|
||||||
}
|
|
||||||
|
|
||||||
NEXTPNR_NAMESPACE_END
|
|
||||||
@ -1,2 +0,0 @@
|
|||||||
#define BINARYFILE 256
|
|
||||||
#define IDR_CHIPDB_1200 103
|
|
||||||
Loading…
Reference in New Issue
Block a user