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interchange: disallow placing cells on sites with clusters

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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-08-05 14:20:25 +02:00
parent 0e83db47a0
commit 78bf5796db
2 changed files with 22 additions and 4 deletions
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23
fpga_interchange/arch.h
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@ -859,6 +859,9 @@ struct Arch : ArchAPI<ArchRanges>
const TileStatus &tile_status = iter->second;
const CellInfo *cell = tile_status.boundcells[bel.index];
auto &bel_data = bel_info(chip_info, bel);
auto &site_status = get_site_status(tile_status, bel_data);
if (cell != nullptr) {
if (!dedicated_interconnect.isBelLocationValid(bel, cell))
return false;
@ -873,14 +876,28 @@ struct Arch : ArchAPI<ArchRanges>
if (!is_cell_valid_constraints(cell, tile_status, explain_constraints)) {
return false;
}
for (auto ci : site_status.cells_in_site) {
if (ci->cluster != ClusterId() && cell->cluster != ClusterId())
continue;
else if (ci->cluster == cell->cluster)
continue;
if (ci->cluster != ClusterId() &&
cluster_info(chip_info, clusters.at(ci->cluster).index).disallow_other_cells)
return false;
if (cell->cluster != ClusterId() &&
cluster_info(chip_info, clusters.at(cell->cluster).index).disallow_other_cells)
return false;
}
}
// Still check site status if cell is nullptr; as other bels in the site could be illegal (for example when
// dedicated paths can no longer be used after ripping up a cell)
auto &bel_data = bel_info(chip_info, bel);
bool site_status = get_site_status(tile_status, bel_data).checkSiteRouting(getCtx(), tile_status);
bool routing_status = site_status.checkSiteRouting(getCtx(), tile_status);
return site_status;
return routing_status;
}
CellInfo *getClusterRootCell(ClusterId cluster) const override;

3
fpga_interchange/chipdb.h
View File

@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
* kExpectedChipInfoVersion
*/
static constexpr int32_t kExpectedChipInfoVersion = 13;
static constexpr int32_t kExpectedChipInfoVersion = 14;
// Flattened site indexing.
//
@ -422,6 +422,7 @@ NPNR_PACKED_STRUCT(struct ClusterPOD {
RelSlice<ChainablePortPOD> chainable_ports;
RelSlice<ClusterCellPortPOD> cluster_cells_map;
uint32_t out_of_site_clusters;
uint32_t disallow_other_cells;
});
NPNR_PACKED_STRUCT(struct ChipInfoPOD {