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interchange: Add nice error for missing cell pins

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-23 15:40:34 +00:00
parent 9ef412c2cc
commit 79400756f5
1 changed files with 3 additions and 0 deletions
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3
fpga_interchange/site_router.cc
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@ -58,6 +58,9 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
for (CellInfo *cell : site_info->cells_in_site) {
BelId bel = cell->bel;
for (const auto &pin_pair : cell->cell_bel_pins) {
if (!cell->ports.count(pin_pair.first))
log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
pin_pair.first.c_str(ctx));
const PortInfo &port = cell->ports.at(pin_pair.first);
NPNR_ASSERT(port.net != nullptr);