From 79400756f5d9d9c751aea93d1071d95073751075 Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 23 Mar 2021 15:40:34 +0000 Subject: [PATCH] interchange: Add nice error for missing cell pins Signed-off-by: gatecat --- fpga_interchange/site_router.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index c470f3f6..3252cac1 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -58,6 +58,9 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info) for (CellInfo *cell : site_info->cells_in_site) { BelId bel = cell->bel; for (const auto &pin_pair : cell->cell_bel_pins) { + if (!cell->ports.count(pin_pair.first)) + log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx), + pin_pair.first.c_str(ctx)); const PortInfo &port = cell->ports.at(pin_pair.first); NPNR_ASSERT(port.net != nullptr);