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Add support for CellInfo->pins in router

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-13 17:52:18 +02:00
parent 1a3d0f2f5d
commit 794fc6df60
2 changed files with 17 additions and 5 deletions
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18
common/route.cc
View File

@ -77,8 +77,13 @@ void route_design(Design *design, bool verbose)
auto src_pos = chip.getBelPosition(src_bel);
auto src_wire = chip.getWireBelPin(
src_bel, portPinFromId(net_info->driver.port));
IdString driver_port = net_info->driver.port;
auto driver_port_it = net_info->driver.cell->pins.find(driver_port);
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
auto src_wire = chip.getWireBelPin(src_bel, portPinFromId(driver_port));
if (src_wire == WireId())
log_error("No wire found for port %s on source bel.\n",
@ -110,8 +115,15 @@ void route_design(Design *design, bool verbose)
chip.estimateDelay(src_pos, dst_pos));
}
IdString user_port = user_it.port;
auto user_port_it = user_it.cell->pins.find(user_port);
if (user_port_it != user_it.cell->pins.end())
user_port = user_port_it->second;
auto dst_wire =
chip.getWireBelPin(dst_bel, portPinFromId(user_it.port));
chip.getWireBelPin(dst_bel, portPinFromId(user_port));
if (dst_wire == WireId())
log_error("No wire found for port %s on destination bel.\n",

4
frontend/json/jsonparse.cc
View File

@ -421,8 +421,8 @@ void json_import_ports(Design *design, const string &modname,
//
// Pick a name for this port
if (is_bus)
this_port.name =
port_info.name.str() + "[" + std::to_string(index) + "]";
this_port.name = port_info.name.str() + "[" +
std::to_string(index) + "]";
else
this_port.name = port_info.name;
this_port.type = port_info.type;