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Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires

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ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
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David Shah 2019-02-25 08:20:32 +00:00 committed by GitHub
commit 7a5699891a
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2 changed files with 24 additions and 0 deletions
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19
ice40/chipdb.py
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@ -954,6 +954,25 @@ def add_bel_ec(ec):
add_pll_clock_output(bel, ec, entry) add_pll_clock_output(bel, ec, entry)
else: else:
extra_cell_config[bel].append(entry) extra_cell_config[bel].append(entry)
if ectype == "MAC16":
if y == 5:
last_dsp_y = 0 # dummy, but the wire is needed
elif y == 10:
last_dsp_y = 5
elif y == 15:
last_dsp_y = 10
elif y == 23:
last_dsp_y = 23
else:
assert False, "unknown DSP y " + str(y)
wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout")
wire_signextout = add_wire(x, y, "dsp/signextout")
wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco")
wire_accumco = add_wire(x, y, "dsp/accumco")
add_bel_input(bel, wire_signextin, "SIGNEXTIN")
add_bel_output(bel, wire_signextout, "SIGNEXTOUT")
add_bel_input(bel, wire_accumci, "ACCUMCI")
add_bel_output(bel, wire_accumco, "ACCUMCO")
cell_timings = {} cell_timings = {}
tmport_to_constids = { tmport_to_constids = {

5
ice40/constids.inc
View File

@ -247,6 +247,11 @@ X(O_6)
X(O_7) X(O_7)
X(O_8) X(O_8)
X(O_9) X(O_9)
X(SIGNEXTIN)
X(SIGNEXTOUT)
X(ACCUMCI)
X(ACCUMCO)
X(CLKHF) X(CLKHF)
X(CLKHFEN) X(CLKHFEN)