From 7b15569c694eb19a982f21746a391415e5930285 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 12 Aug 2018 20:29:04 -0700 Subject: [PATCH] Use general pin names for QUARTER_SLICE --- xc7/arch.cc | 31 ++++++++++++++------------ xc7/archdefs.h | 2 +- xc7/cells.cc | 58 ++++++++++++++++++++++++------------------------ xc7/constids.inc | 13 ++--------- xc7/pack.cc | 8 +++---- 5 files changed, 53 insertions(+), 59 deletions(-) diff --git a/xc7/arch.cc b/xc7/arch.cc index ce13edeb..caee112f 100644 --- a/xc7/arch.cc +++ b/xc7/arch.cc @@ -197,7 +197,10 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const WireId ret; const auto& site = torc_sites->getSite(bel.index); - ret.index = site.getPinTilewire(pin.str(this)); + auto pin_name = pin.str(this); + if (bel_index_to_type[bel.index] == id_QUARTER_SLICE) + pin_name[0] = bel.pos; + ret.index = site.getPinTilewire(pin_name); // NPNR_ASSERT(bel != BelId()); // @@ -699,8 +702,8 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort { if (cell->type == id_QUARTER_SLICE) { - if (fromPort.index >= id_A1.index && fromPort.index <= id_A6.index) - return toPort == id_A || toPort == id_AQ; + if (fromPort.index >= id_I1.index && fromPort.index <= id_I6.index) + return toPort == id_O || toPort == id_OQ; } else if (cell->type == id_BUFGCTRL) { @@ -717,11 +720,11 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id return TMG_CLOCK_INPUT; if (port == id_CIN) return TMG_COMB_INPUT; - if (port == id_COUT || port == id_A) + if (port == id_COUT || port == id_O) return TMG_COMB_OUTPUT; if (cell->lcInfo.dffEnable) { clockPort = id_CLK; - if (port == id_AQ) + if (port == id_OQ) return TMG_REGISTER_OUTPUT; else return TMG_REGISTER_INPUT; @@ -784,15 +787,15 @@ void Arch::assignCellInfo(CellInfo *cell) cell->lcInfo.clk = get_net_or_empty(cell, id_CLK); cell->lcInfo.cen = get_net_or_empty(cell, id_CEN); cell->lcInfo.sr = get_net_or_empty(cell, id_SR); - cell->lcInfo.inputCount = 0; - if (get_net_or_empty(cell, id_I0)) - cell->lcInfo.inputCount++; - if (get_net_or_empty(cell, id_I1)) - cell->lcInfo.inputCount++; - if (get_net_or_empty(cell, id_I2)) - cell->lcInfo.inputCount++; - if (get_net_or_empty(cell, id_I3)) - cell->lcInfo.inputCount++; +// cell->lcInfo.inputCount = 0; +// if (get_net_or_empty(cell, id_I0)) +// cell->lcInfo.inputCount++; +// if (get_net_or_empty(cell, id_I1)) +// cell->lcInfo.inputCount++; +// if (get_net_or_empty(cell, id_I2)) +// cell->lcInfo.inputCount++; +// if (get_net_or_empty(cell, id_I3)) +// cell->lcInfo.inputCount++; } } diff --git a/xc7/archdefs.h b/xc7/archdefs.h index bfeadea4..9c0efc70 100644 --- a/xc7/archdefs.h +++ b/xc7/archdefs.h @@ -67,7 +67,7 @@ enum ConstIds struct BelId { SiteIndex index = SiteIndex(-1); - enum bel : int8_t { NOT_APPLICABLE, A, B, C, D } pos = NOT_APPLICABLE; + enum bel : int8_t { NOT_APPLICABLE, A='A', B='B', C='C', D='D' } pos = NOT_APPLICABLE; bool operator==(const BelId &other) const { return index == other.index && pos == pos; } bool operator!=(const BelId &other) const { return index != other.index || pos != pos; } diff --git a/xc7/cells.cc b/xc7/cells.cc index c36d1443..ad0ab420 100644 --- a/xc7/cells.cc +++ b/xc7/cells.cc @@ -53,21 +53,21 @@ std::unique_ptr create_ice_cell(Context *ctx, IdString type, std::stri new_cell->params[ctx->id("CIN_CONST")] = "0"; new_cell->params[ctx->id("CIN_SET")] = "0"; - add_port(ctx, new_cell.get(), "A1", PORT_IN); - add_port(ctx, new_cell.get(), "A2", PORT_IN); - add_port(ctx, new_cell.get(), "A3", PORT_IN); - add_port(ctx, new_cell.get(), "A4", PORT_IN); - add_port(ctx, new_cell.get(), "A5", PORT_IN); - add_port(ctx, new_cell.get(), "A6", PORT_IN); + add_port(ctx, new_cell.get(), "I1", PORT_IN); + add_port(ctx, new_cell.get(), "I2", PORT_IN); + add_port(ctx, new_cell.get(), "I3", PORT_IN); + add_port(ctx, new_cell.get(), "I4", PORT_IN); + add_port(ctx, new_cell.get(), "I5", PORT_IN); + add_port(ctx, new_cell.get(), "I6", PORT_IN); add_port(ctx, new_cell.get(), "CIN", PORT_IN); add_port(ctx, new_cell.get(), "CLK", PORT_IN); add_port(ctx, new_cell.get(), "CE", PORT_IN); add_port(ctx, new_cell.get(), "SR", PORT_IN); - add_port(ctx, new_cell.get(), "A", PORT_OUT); - add_port(ctx, new_cell.get(), "AQ", PORT_OUT); - add_port(ctx, new_cell.get(), "AMUX", PORT_OUT); + add_port(ctx, new_cell.get(), "O", PORT_OUT); + add_port(ctx, new_cell.get(), "OQ", PORT_OUT); + add_port(ctx, new_cell.get(), "OMUX", PORT_OUT); add_port(ctx, new_cell.get(), "COUT", PORT_OUT); } else if (type == ctx->id("IOBUF")) { new_cell->type = id_IOB33S; @@ -259,19 +259,19 @@ std::unique_ptr create_ice_cell(Context *ctx, IdString type, std::stri void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff) { lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")]; - replace_port(lut, ctx->id("I0"), lc, ctx->id("A1")); - if (get_net_or_empty(lut, ctx->id("I1"))) - replace_port(lut, ctx->id("I1"), lc, ctx->id("A2")); - if (get_net_or_empty(lut, ctx->id("I2"))) - replace_port(lut, ctx->id("I2"), lc, ctx->id("A3")); - if (get_net_or_empty(lut, ctx->id("I3"))) - replace_port(lut, ctx->id("I3"), lc, ctx->id("A4")); - if (get_net_or_empty(lut, ctx->id("I4"))) - replace_port(lut, ctx->id("I4"), lc, ctx->id("A5")); - if (get_net_or_empty(lut, ctx->id("I5"))) - replace_port(lut, ctx->id("I5"), lc, ctx->id("A6")); + replace_port(lut, ctx->id("I0"), lc, id_I1); + if (get_net_or_empty(lut, id_I1)) + replace_port(lut, id_I1, lc, id_I2); + if (get_net_or_empty(lut, id_I2)) + replace_port(lut, id_I2, lc, id_I3); + if (get_net_or_empty(lut, id_I3)) + replace_port(lut, id_I3, lc, id_I4); + if (get_net_or_empty(lut, id_I4)) + replace_port(lut, id_I4, lc, id_I5); + if (get_net_or_empty(lut, id_I5)) + replace_port(lut, id_I5, lc, id_I6); if (no_dff) { - replace_port(lut, ctx->id("O"), lc, ctx->id("A")); + replace_port(lut, id_O, lc, id_O); lc->params[ctx->id("DFF_ENABLE")] = "0"; } } @@ -318,10 +318,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l if (pass_thru_lut) { lc->params[ctx->id("LUT_INIT")] = "2"; - replace_port(dff, ctx->id("D"), lc, ctx->id("A1")); + replace_port(dff, ctx->id("D"), lc, id_I1); } - replace_port(dff, ctx->id("Q"), lc, ctx->id("AQ")); + replace_port(dff, ctx->id("Q"), lc, id_OQ); } void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio) @@ -331,25 +331,25 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio) auto pu_attr = nxio->attrs.find(ctx->id("PULLUP")); if (pu_attr != nxio->attrs.end()) sbio->params[ctx->id("PULLUP")] = pu_attr->second; - replace_port(nxio, ctx->id("O"), sbio, ctx->id("I")); + replace_port(nxio, id_O, sbio, id_I); } else if (nxio->type == ctx->id("$nextpnr_obuf")) { sbio->params[ctx->id("PIN_TYPE")] = "25"; - replace_port(nxio, ctx->id("I"), sbio, ctx->id("O")); + replace_port(nxio, id_I, sbio, id_O); } else if (nxio->type == ctx->id("$nextpnr_iobuf")) { // N.B. tristate will be dealt with below sbio->params[ctx->id("PIN_TYPE")] = "25"; - replace_port(nxio, ctx->id("I"), sbio, ctx->id("O")); - replace_port(nxio, ctx->id("O"), sbio, ctx->id("I")); + replace_port(nxio, id_I, sbio, id_O); + replace_port(nxio, id_O, sbio, id_I); } else { NPNR_ASSERT(false); } - NetInfo *donet = sbio->ports.at(ctx->id("O")).net; + NetInfo *donet = sbio->ports.at(id_O).net; CellInfo *tbuf = net_driven_by( ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); }, ctx->id("Y")); if (tbuf) { sbio->params[ctx->id("PIN_TYPE")] = "41"; - replace_port(tbuf, ctx->id("A"), sbio, ctx->id("O")); + replace_port(tbuf, ctx->id("A"), sbio, id_O); replace_port(tbuf, ctx->id("E"), sbio, ctx->id("OUTPUT_ENABLE")); ctx->nets.erase(donet->name); if (!donet->users.empty()) diff --git a/xc7/constids.inc b/xc7/constids.inc index 632524de..2fa867a0 100644 --- a/xc7/constids.inc +++ b/xc7/constids.inc @@ -1,10 +1,11 @@ // pin and port names -X(I0) +//X(I0) X(I1) X(I2) X(I3) X(I4) X(I5) +X(I6) X(O) X(OQ) X(OMUX) @@ -441,16 +442,6 @@ X(NEG_CLK) X(I) -X(A1) -X(A2) -X(A3) -X(A4) -X(A5) -X(A6) -X(A) -X(AQ) -X(AMUX) - X(LUT1) X(LUT2) X(LUT3) diff --git a/xc7/pack.cc b/xc7/pack.cc index 1b2765a0..1e27f8a3 100644 --- a/xc7/pack.cc +++ b/xc7/pack.cc @@ -336,16 +336,16 @@ static void pack_constants(Context *ctx) std::unique_ptr gnd_net = std::unique_ptr(new NetInfo); gnd_net->name = ctx->id("$PACKER_GND_NET"); gnd_net->driver.cell = gnd_cell.get(); - gnd_net->driver.port = ctx->id("A"); - gnd_cell->ports.at(ctx->id("A")).net = gnd_net.get(); + gnd_net->driver.port = id_O; + gnd_cell->ports.at(id_O).net = gnd_net.get(); std::unique_ptr vcc_cell = create_ice_cell(ctx, ctx->id("XC7_LC"), "$PACKER_VCC"); vcc_cell->params[ctx->id("LUT_INIT")] = "1"; std::unique_ptr vcc_net = std::unique_ptr(new NetInfo); vcc_net->name = ctx->id("$PACKER_VCC_NET"); vcc_net->driver.cell = vcc_cell.get(); - vcc_net->driver.port = ctx->id("A"); - vcc_cell->ports.at(ctx->id("A")).net = vcc_net.get(); + vcc_net->driver.port = id_O; + vcc_cell->ports.at(id_O).net = vcc_net.get(); std::vector dead_nets;