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Use general pin names for QUARTER_SLICE

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This commit is contained in:
Eddie Hung 2018-08-12 20:29:04 -07:00
parent 56b7299cca
commit 7b15569c69
5 changed files with 53 additions and 59 deletions
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31
xc7/arch.cc
View File

@ -197,7 +197,10 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
WireId ret; WireId ret;
const auto& site = torc_sites->getSite(bel.index); const auto& site = torc_sites->getSite(bel.index);
ret.index = site.getPinTilewire(pin.str(this)); auto pin_name = pin.str(this);
if (bel_index_to_type[bel.index] == id_QUARTER_SLICE)
pin_name[0] = bel.pos;
ret.index = site.getPinTilewire(pin_name);
// NPNR_ASSERT(bel != BelId()); // NPNR_ASSERT(bel != BelId());
// //
@ -699,8 +702,8 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
{ {
if (cell->type == id_QUARTER_SLICE) if (cell->type == id_QUARTER_SLICE)
{ {
if (fromPort.index >= id_A1.index && fromPort.index <= id_A6.index) if (fromPort.index >= id_I1.index && fromPort.index <= id_I6.index)
return toPort == id_A || toPort == id_AQ; return toPort == id_O || toPort == id_OQ;
} }
else if (cell->type == id_BUFGCTRL) else if (cell->type == id_BUFGCTRL)
{ {
@ -717,11 +720,11 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
return TMG_CLOCK_INPUT; return TMG_CLOCK_INPUT;
if (port == id_CIN) if (port == id_CIN)
return TMG_COMB_INPUT; return TMG_COMB_INPUT;
if (port == id_COUT || port == id_A) if (port == id_COUT || port == id_O)
return TMG_COMB_OUTPUT; return TMG_COMB_OUTPUT;
if (cell->lcInfo.dffEnable) { if (cell->lcInfo.dffEnable) {
clockPort = id_CLK; clockPort = id_CLK;
if (port == id_AQ) if (port == id_OQ)
return TMG_REGISTER_OUTPUT; return TMG_REGISTER_OUTPUT;
else else
return TMG_REGISTER_INPUT; return TMG_REGISTER_INPUT;
@ -784,15 +787,15 @@ void Arch::assignCellInfo(CellInfo *cell)
cell->lcInfo.clk = get_net_or_empty(cell, id_CLK); cell->lcInfo.clk = get_net_or_empty(cell, id_CLK);
cell->lcInfo.cen = get_net_or_empty(cell, id_CEN); cell->lcInfo.cen = get_net_or_empty(cell, id_CEN);
cell->lcInfo.sr = get_net_or_empty(cell, id_SR); cell->lcInfo.sr = get_net_or_empty(cell, id_SR);
cell->lcInfo.inputCount = 0; // cell->lcInfo.inputCount = 0;
if (get_net_or_empty(cell, id_I0)) // if (get_net_or_empty(cell, id_I0))
cell->lcInfo.inputCount++; // cell->lcInfo.inputCount++;
if (get_net_or_empty(cell, id_I1)) // if (get_net_or_empty(cell, id_I1))
cell->lcInfo.inputCount++; // cell->lcInfo.inputCount++;
if (get_net_or_empty(cell, id_I2)) // if (get_net_or_empty(cell, id_I2))
cell->lcInfo.inputCount++; // cell->lcInfo.inputCount++;
if (get_net_or_empty(cell, id_I3)) // if (get_net_or_empty(cell, id_I3))
cell->lcInfo.inputCount++; // cell->lcInfo.inputCount++;
} }
} }

2
xc7/archdefs.h
View File

@ -67,7 +67,7 @@ enum ConstIds
struct BelId struct BelId
{ {
SiteIndex index = SiteIndex(-1); SiteIndex index = SiteIndex(-1);
enum bel : int8_t { NOT_APPLICABLE, A, B, C, D } pos = NOT_APPLICABLE; enum bel : int8_t { NOT_APPLICABLE, A='A', B='B', C='C', D='D' } pos = NOT_APPLICABLE;
bool operator==(const BelId &other) const { return index == other.index && pos == pos; } bool operator==(const BelId &other) const { return index == other.index && pos == pos; }
bool operator!=(const BelId &other) const { return index != other.index || pos != pos; } bool operator!=(const BelId &other) const { return index != other.index || pos != pos; }

58
xc7/cells.cc
View File

@ -53,21 +53,21 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
new_cell->params[ctx->id("CIN_CONST")] = "0"; new_cell->params[ctx->id("CIN_CONST")] = "0";
new_cell->params[ctx->id("CIN_SET")] = "0"; new_cell->params[ctx->id("CIN_SET")] = "0";
add_port(ctx, new_cell.get(), "A1", PORT_IN); add_port(ctx, new_cell.get(), "I1", PORT_IN);
add_port(ctx, new_cell.get(), "A2", PORT_IN); add_port(ctx, new_cell.get(), "I2", PORT_IN);
add_port(ctx, new_cell.get(), "A3", PORT_IN); add_port(ctx, new_cell.get(), "I3", PORT_IN);
add_port(ctx, new_cell.get(), "A4", PORT_IN); add_port(ctx, new_cell.get(), "I4", PORT_IN);
add_port(ctx, new_cell.get(), "A5", PORT_IN); add_port(ctx, new_cell.get(), "I5", PORT_IN);
add_port(ctx, new_cell.get(), "A6", PORT_IN); add_port(ctx, new_cell.get(), "I6", PORT_IN);
add_port(ctx, new_cell.get(), "CIN", PORT_IN); add_port(ctx, new_cell.get(), "CIN", PORT_IN);
add_port(ctx, new_cell.get(), "CLK", PORT_IN); add_port(ctx, new_cell.get(), "CLK", PORT_IN);
add_port(ctx, new_cell.get(), "CE", PORT_IN); add_port(ctx, new_cell.get(), "CE", PORT_IN);
add_port(ctx, new_cell.get(), "SR", PORT_IN); add_port(ctx, new_cell.get(), "SR", PORT_IN);
add_port(ctx, new_cell.get(), "A", PORT_OUT); add_port(ctx, new_cell.get(), "O", PORT_OUT);
add_port(ctx, new_cell.get(), "AQ", PORT_OUT); add_port(ctx, new_cell.get(), "OQ", PORT_OUT);
add_port(ctx, new_cell.get(), "AMUX", PORT_OUT); add_port(ctx, new_cell.get(), "OMUX", PORT_OUT);
add_port(ctx, new_cell.get(), "COUT", PORT_OUT); add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
} else if (type == ctx->id("IOBUF")) { } else if (type == ctx->id("IOBUF")) {
new_cell->type = id_IOB33S; new_cell->type = id_IOB33S;
@ -259,19 +259,19 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff) void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
{ {
lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")]; lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")];
replace_port(lut, ctx->id("I0"), lc, ctx->id("A1")); replace_port(lut, ctx->id("I0"), lc, id_I1);
if (get_net_or_empty(lut, ctx->id("I1"))) if (get_net_or_empty(lut, id_I1))
replace_port(lut, ctx->id("I1"), lc, ctx->id("A2")); replace_port(lut, id_I1, lc, id_I2);
if (get_net_or_empty(lut, ctx->id("I2"))) if (get_net_or_empty(lut, id_I2))
replace_port(lut, ctx->id("I2"), lc, ctx->id("A3")); replace_port(lut, id_I2, lc, id_I3);
if (get_net_or_empty(lut, ctx->id("I3"))) if (get_net_or_empty(lut, id_I3))
replace_port(lut, ctx->id("I3"), lc, ctx->id("A4")); replace_port(lut, id_I3, lc, id_I4);
if (get_net_or_empty(lut, ctx->id("I4"))) if (get_net_or_empty(lut, id_I4))
replace_port(lut, ctx->id("I4"), lc, ctx->id("A5")); replace_port(lut, id_I4, lc, id_I5);
if (get_net_or_empty(lut, ctx->id("I5"))) if (get_net_or_empty(lut, id_I5))
replace_port(lut, ctx->id("I5"), lc, ctx->id("A6")); replace_port(lut, id_I5, lc, id_I6);
if (no_dff) { if (no_dff) {
replace_port(lut, ctx->id("O"), lc, ctx->id("A")); replace_port(lut, id_O, lc, id_O);
lc->params[ctx->id("DFF_ENABLE")] = "0"; lc->params[ctx->id("DFF_ENABLE")] = "0";
} }
} }
@ -318,10 +318,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (pass_thru_lut) { if (pass_thru_lut) {
lc->params[ctx->id("LUT_INIT")] = "2"; lc->params[ctx->id("LUT_INIT")] = "2";
replace_port(dff, ctx->id("D"), lc, ctx->id("A1")); replace_port(dff, ctx->id("D"), lc, id_I1);
} }
replace_port(dff, ctx->id("Q"), lc, ctx->id("AQ")); replace_port(dff, ctx->id("Q"), lc, id_OQ);
} }
void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio) void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio)
@ -331,25 +331,25 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio)
auto pu_attr = nxio->attrs.find(ctx->id("PULLUP")); auto pu_attr = nxio->attrs.find(ctx->id("PULLUP"));
if (pu_attr != nxio->attrs.end()) if (pu_attr != nxio->attrs.end())
sbio->params[ctx->id("PULLUP")] = pu_attr->second; sbio->params[ctx->id("PULLUP")] = pu_attr->second;
replace_port(nxio, ctx->id("O"), sbio, ctx->id("I")); replace_port(nxio, id_O, sbio, id_I);
} else if (nxio->type == ctx->id("$nextpnr_obuf")) { } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
sbio->params[ctx->id("PIN_TYPE")] = "25"; sbio->params[ctx->id("PIN_TYPE")] = "25";
replace_port(nxio, ctx->id("I"), sbio, ctx->id("O")); replace_port(nxio, id_I, sbio, id_O);
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) { } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
// N.B. tristate will be dealt with below // N.B. tristate will be dealt with below
sbio->params[ctx->id("PIN_TYPE")] = "25"; sbio->params[ctx->id("PIN_TYPE")] = "25";
replace_port(nxio, ctx->id("I"), sbio, ctx->id("O")); replace_port(nxio, id_I, sbio, id_O);
replace_port(nxio, ctx->id("O"), sbio, ctx->id("I")); replace_port(nxio, id_O, sbio, id_I);
} else { } else {
NPNR_ASSERT(false); NPNR_ASSERT(false);
} }
NetInfo *donet = sbio->ports.at(ctx->id("O")).net; NetInfo *donet = sbio->ports.at(id_O).net;
CellInfo *tbuf = net_driven_by( CellInfo *tbuf = net_driven_by(
ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); }, ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
ctx->id("Y")); ctx->id("Y"));
if (tbuf) { if (tbuf) {
sbio->params[ctx->id("PIN_TYPE")] = "41"; sbio->params[ctx->id("PIN_TYPE")] = "41";
replace_port(tbuf, ctx->id("A"), sbio, ctx->id("O")); replace_port(tbuf, ctx->id("A"), sbio, id_O);
replace_port(tbuf, ctx->id("E"), sbio, ctx->id("OUTPUT_ENABLE")); replace_port(tbuf, ctx->id("E"), sbio, ctx->id("OUTPUT_ENABLE"));
ctx->nets.erase(donet->name); ctx->nets.erase(donet->name);
if (!donet->users.empty()) if (!donet->users.empty())

13
xc7/constids.inc
View File

@ -1,10 +1,11 @@
// pin and port names // pin and port names
X(I0) //X(I0)
X(I1) X(I1)
X(I2) X(I2)
X(I3) X(I3)
X(I4) X(I4)
X(I5) X(I5)
X(I6)
X(O) X(O)
X(OQ) X(OQ)
X(OMUX) X(OMUX)
@ -441,16 +442,6 @@ X(NEG_CLK)
X(I) X(I)
X(A1)
X(A2)
X(A3)
X(A4)
X(A5)
X(A6)
X(A)
X(AQ)
X(AMUX)
X(LUT1) X(LUT1)
X(LUT2) X(LUT2)
X(LUT3) X(LUT3)

8
xc7/pack.cc
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@ -336,16 +336,16 @@ static void pack_constants(Context *ctx)
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo); std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
gnd_net->name = ctx->id("$PACKER_GND_NET"); gnd_net->name = ctx->id("$PACKER_GND_NET");
gnd_net->driver.cell = gnd_cell.get(); gnd_net->driver.cell = gnd_cell.get();
gnd_net->driver.port = ctx->id("A"); gnd_net->driver.port = id_O;
gnd_cell->ports.at(ctx->id("A")).net = gnd_net.get(); gnd_cell->ports.at(id_O).net = gnd_net.get();
std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("XC7_LC"), "$PACKER_VCC"); std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("XC7_LC"), "$PACKER_VCC");
vcc_cell->params[ctx->id("LUT_INIT")] = "1"; vcc_cell->params[ctx->id("LUT_INIT")] = "1";
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo); std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
vcc_net->name = ctx->id("$PACKER_VCC_NET"); vcc_net->name = ctx->id("$PACKER_VCC_NET");
vcc_net->driver.cell = vcc_cell.get(); vcc_net->driver.cell = vcc_cell.get();
vcc_net->driver.port = ctx->id("A"); vcc_net->driver.port = id_O;
vcc_cell->ports.at(ctx->id("A")).net = vcc_net.get(); vcc_cell->ports.at(id_O).net = vcc_net.get();
std::vector<IdString> dead_nets; std::vector<IdString> dead_nets;