generic: Use IdStringList for all arch object names

Signed-off-by: D. Shah <dave@ds0.me>

common/nextpnr.h

@@ -243,6 +243,21 @@ struct IdStringList
     const IdString &operator[](size_t idx) const { return ids[idx]; }
     bool operator==(const IdStringList &other) const { return ids == other.ids; }
     bool operator!=(const IdStringList &other) const { return ids != other.ids; }
+    bool operator<(const IdStringList &other) const
+    {
+        if (size() > other.size())
+            return false;
+        if (size() < other.size())
+            return true;
+        for (size_t i = 0; i < size(); i++) {
+            IdString a = ids[i], b = other[i];
+            if (a.index < b.index)
+                return true;
+            if (a.index > b.index)
+                return false;
+        }
+        return false;
+    }
 };
 
 NEXTPNR_NAMESPACE_END

common/pybindings.h

@@ -74,6 +74,18 @@ template <> struct string_converter<const IdString>
     inline std::string to_str(Context *ctx, IdString id) { return id.str(ctx); }
 };
 
+template <> struct string_converter<IdStringList>
+{
+    IdStringList from_str(Context *ctx, std::string name) { return IdStringList::parse(ctx, name); }
+    std::string to_str(Context *ctx, const IdStringList &id) { return id.str(ctx); }
+};
+
+template <> struct string_converter<const IdStringList>
+{
+    IdStringList from_str(Context *ctx, std::string name) { return IdStringList::parse(ctx, name); }
+    std::string to_str(Context *ctx, const IdStringList &id) { return id.str(ctx); }
+};
+
 } // namespace PythonConversion
 
 NEXTPNR_NAMESPACE_END

common/timing_opt.cc

@@ -59,7 +59,7 @@ template <> struct hash<std::pair<int, NEXTPNR_NAMESPACE_PREFIX BelId>>
         return seed;
     }
 };
-#if !defined(ARCH_GENERIC) && !defined(ARCH_GOWIN)
+#if !defined(ARCH_GOWIN)
 template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId>>
 {
     std::size_t

generic/arch.cc

@@ -28,31 +28,31 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-WireInfo &Arch::wire_info(IdString wire)
+WireInfo &Arch::wire_info(IdStringList wire)
 {
     auto w = wires.find(wire);
     if (w == wires.end())
-        NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(this));
+        NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(getCtx()));
     return w->second;
 }
 
-PipInfo &Arch::pip_info(IdString pip)
+PipInfo &Arch::pip_info(IdStringList pip)
 {
     auto p = pips.find(pip);
     if (p == pips.end())
-        NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(this));
+        NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(getCtx()));
     return p->second;
 }
 
-BelInfo &Arch::bel_info(IdString bel)
+BelInfo &Arch::bel_info(IdStringList bel)
 {
     auto b = bels.find(bel);
     if (b == bels.end())
-        NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(this));
+        NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(getCtx()));
     return b->second;
 }
 
-void Arch::addWire(IdString name, IdString type, int x, int y)
+void Arch::addWire(IdStringList name, IdString type, int x, int y)
 {
     NPNR_ASSERT(wires.count(name) == 0);
     WireInfo &wi = wires[name];
@@ -64,7 +64,8 @@ void Arch::addWire(IdString name, IdString type, int x, int y)
     wire_ids.push_back(name);
 }
 
-void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc)
+void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay,
+                  Loc loc)
 {
     NPNR_ASSERT(pips.count(name) == 0);
     PipInfo &pi = pips[name];
@@ -90,7 +91,7 @@ void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWi
     tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
 }
 
-void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
+void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb)
 {
     NPNR_ASSERT(bels.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
@@ -124,7 +125,7 @@ void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
     tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
 }
 
-void Arch::addBelInput(IdString bel, IdString name, IdString wire)
+void Arch::addBelInput(IdStringList bel, IdString name, IdStringList wire)
 {
     NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
     PinInfo &pi = bel_info(bel).pins[name];
@@ -136,7 +137,7 @@ void Arch::addBelInput(IdString bel, IdString name, IdString wire)
     wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
-void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
+void Arch::addBelOutput(IdStringList bel, IdString name, IdStringList wire)
 {
     NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
     PinInfo &pi = bel_info(bel).pins[name];
@@ -148,7 +149,7 @@ void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
     wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
-void Arch::addBelInout(IdString bel, IdString name, IdString wire)
+void Arch::addBelInout(IdStringList bel, IdString name, IdStringList wire)
 {
     NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
     PinInfo &pi = bel_info(bel).pins[name];
@@ -160,13 +161,13 @@ void Arch::addBelInout(IdString bel, IdString name, IdString wire)
     wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
-void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); }
+void Arch::addGroupBel(IdStringList group, IdStringList bel) { groups[group].bels.push_back(bel); }
 
-void Arch::addGroupWire(IdString group, IdString wire) { groups[group].wires.push_back(wire); }
+void Arch::addGroupWire(IdStringList group, IdStringList wire) { groups[group].wires.push_back(wire); }
 
-void Arch::addGroupPip(IdString group, IdString pip) { groups[group].pips.push_back(pip); }
+void Arch::addGroupPip(IdStringList group, IdStringList pip) { groups[group].pips.push_back(pip); }
 
-void Arch::addGroupGroup(IdString group, IdString grp) { groups[group].groups.push_back(grp); }
+void Arch::addGroupGroup(IdStringList group, IdStringList grp) { groups[group].groups.push_back(grp); }
 
 void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
 {
@@ -198,11 +199,14 @@ void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
     refreshUiGroup(group);
 }
 
-void Arch::setWireAttr(IdString wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
+void Arch::setWireAttr(IdStringList wire, IdString key, const std::string &value)
+{
+    wire_info(wire).attrs[key] = value;
+}
 
-void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
+void Arch::setPipAttr(IdStringList pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
 
-void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
+void Arch::setBelAttr(IdStringList bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
 
 void Arch::setLutK(int K) { args.K = K; }
 
@@ -212,9 +216,12 @@ void Arch::setDelayScaling(double scale, double offset)
     args.delayOffset = offset;
 }
 
-void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
+void Arch::addCellTimingClock(IdStringList cell, IdString port)
+{
+    cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT;
+}
 
-void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay)
+void Arch::addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay)
 {
     if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE)
         cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT;
@@ -223,7 +230,7 @@ void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort,
     cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay;
 }
 
-void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
+void Arch::addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
 {
     TimingClockingInfo ci;
     ci.clock_port = clock;
@@ -234,7 +241,7 @@ void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock,
     cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT;
 }
 
-void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq)
+void Arch::addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq)
 {
     TimingClockingInfo ci;
     ci.clock_port = clock;
@@ -256,14 +263,14 @@ void IdString::initialize_arch(const BaseCtx *ctx) {}
 
 // ---------------------------------------------------------------
 
-BelId Arch::getBelByName(IdString name) const
+BelId Arch::getBelByName(IdStringList name) const
 {
     if (bels.count(name))
         return name;
     return BelId();
 }
 
-IdString Arch::getBelName(BelId bel) const { return bel; }
+IdStringList Arch::getBelName(BelId bel) const { return bel; }
 
 Loc Arch::getBelLocation(BelId bel) const
 {
@@ -321,7 +328,7 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
 {
     const auto &bdata = bels.at(bel);
     if (!bdata.pins.count(pin))
-        log_error("bel '%s' has no pin '%s'\n", bel.c_str(this), pin.c_str(this));
+        log_error("bel '%s' has no pin '%s'\n", getCtx()->nameOfBel(bel), pin.c_str(this));
     return bdata.pins.at(pin).wire;
 }
 
@@ -337,14 +344,14 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
 
 // ---------------------------------------------------------------
 
-WireId Arch::getWireByName(IdString name) const
+WireId Arch::getWireByName(IdStringList name) const
 {
     if (wires.count(name))
         return name;
     return WireId();
 }
 
-IdString Arch::getWireName(WireId wire) const { return wire; }
+IdStringList Arch::getWireName(WireId wire) const { return wire; }
 
 IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; }
 
@@ -391,14 +398,14 @@ const std::vector<WireId> &Arch::getWires() const { return wire_ids; }
 
 // ---------------------------------------------------------------
 
-PipId Arch::getPipByName(IdString name) const
+PipId Arch::getPipByName(IdStringList name) const
 {
     if (pips.count(name))
         return name;
     return PipId();
 }
 
-IdString Arch::getPipName(PipId pip) const { return pip; }
+IdStringList Arch::getPipName(PipId pip) const { return pip; }
 
 IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
 
@@ -455,9 +462,9 @@ const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wires.
 
 // ---------------------------------------------------------------
 
-GroupId Arch::getGroupByName(IdString name) const { return name; }
+GroupId Arch::getGroupByName(IdStringList name) const { return name; }
 
-IdString Arch::getGroupName(GroupId group) const { return group; }
+IdStringList Arch::getGroupName(GroupId group) const { return group; }
 
 std::vector<GroupId> Arch::getGroups() const
 {
@@ -582,8 +589,7 @@ bool Arch::route()
 const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
 {
     if (!decal_graphics.count(decal)) {
-        std::cerr << "No decal named " << decal.str(this) << std::endl;
+        std::cerr << "No decal named " << decal.str(getCtx()) << std::endl;
-        log_error("No decal named %s!\n", decal.c_str(this));
     }
     return decal_graphics.at(decal);
 }

generic/arch.h

@@ -36,7 +36,8 @@ struct WireInfo;
 
 struct PipInfo
 {
-    IdString name, type;
+    IdStringList name;
+    IdString type;
     std::map<IdString, std::string> attrs;
     NetInfo *bound_net;
     WireId srcWire, dstWire;
@@ -47,7 +48,8 @@ struct PipInfo
 
 struct WireInfo
 {
-    IdString name, type;
+    IdStringList name;
+    IdString type;
     std::map<IdString, std::string> attrs;
     NetInfo *bound_net;
     std::vector<PipId> downhill, uphill;
@@ -60,14 +62,15 @@ struct WireInfo
 
 struct PinInfo
 {
-    IdString name;
+    IdStringList name;
     WireId wire;
     PortType type;
 };
 
 struct BelInfo
 {
-    IdString name, type;
+    IdStringList name;
+    IdString type;
     std::map<IdString, std::string> attrs;
     CellInfo *bound_cell;
     std::unordered_map<IdString, PinInfo> pins;
@@ -78,7 +81,7 @@ struct BelInfo
 
 struct GroupInfo
 {
-    IdString name;
+    IdStringList name;
     std::vector<BelId> bels;
     std::vector<WireId> wires;
     std::vector<PipId> pips;
@@ -117,17 +120,17 @@ struct Arch : BaseCtx
 {
     std::string chipName;
 
-    std::unordered_map<IdString, WireInfo> wires;
+    std::unordered_map<IdStringList, WireInfo> wires;
-    std::unordered_map<IdString, PipInfo> pips;
+    std::unordered_map<IdStringList, PipInfo> pips;
-    std::unordered_map<IdString, BelInfo> bels;
+    std::unordered_map<IdStringList, BelInfo> bels;
     std::unordered_map<GroupId, GroupInfo> groups;
 
     // These functions include useful errors if not found
-    WireInfo &wire_info(IdString wire);
+    WireInfo &wire_info(IdStringList wire);
-    PipInfo &pip_info(IdString wire);
+    PipInfo &pip_info(IdStringList wire);
-    BelInfo &bel_info(IdString wire);
+    BelInfo &bel_info(IdStringList wire);
 
-    std::vector<IdString> bel_ids, wire_ids, pip_ids;
+    std::vector<IdStringList> bel_ids, wire_ids, pip_ids;
 
     std::unordered_map<Loc, BelId> bel_by_loc;
     std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
@@ -138,20 +141,20 @@ struct Arch : BaseCtx
     std::vector<std::vector<int>> tileBelDimZ;
     std::vector<std::vector<int>> tilePipDimZ;
 
-    std::unordered_map<IdString, CellTiming> cellTiming;
+    std::unordered_map<IdStringList, CellTiming> cellTiming;
 
-    void addWire(IdString name, IdString type, int x, int y);
+    void addWire(IdStringList name, IdString type, int x, int y);
-    void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
+    void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc);
 
-    void addBel(IdString name, IdString type, Loc loc, bool gb);
+    void addBel(IdStringList name, IdString type, Loc loc, bool gb);
-    void addBelInput(IdString bel, IdString name, IdString wire);
+    void addBelInput(IdStringList bel, IdString name, IdStringList wire);
-    void addBelOutput(IdString bel, IdString name, IdString wire);
+    void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
-    void addBelInout(IdString bel, IdString name, IdString wire);
+    void addBelInout(IdStringList bel, IdString name, IdStringList wire);
 
-    void addGroupBel(IdString group, IdString bel);
+    void addGroupBel(IdStringList group, IdStringList bel);
-    void addGroupWire(IdString group, IdString wire);
+    void addGroupWire(IdStringList group, IdStringList wire);
-    void addGroupPip(IdString group, IdString pip);
+    void addGroupPip(IdStringList group, IdStringList pip);
-    void addGroupGroup(IdString group, IdString grp);
+    void addGroupGroup(IdStringList group, IdStringList grp);
 
     void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
     void setWireDecal(WireId wire, DecalXY decalxy);
@@ -159,17 +162,17 @@ struct Arch : BaseCtx
     void setBelDecal(BelId bel, DecalXY decalxy);
     void setGroupDecal(GroupId group, DecalXY decalxy);
 
-    void setWireAttr(IdString wire, IdString key, const std::string &value);
+    void setWireAttr(IdStringList wire, IdString key, const std::string &value);
-    void setPipAttr(IdString pip, IdString key, const std::string &value);
+    void setPipAttr(IdStringList pip, IdString key, const std::string &value);
-    void setBelAttr(IdString bel, IdString key, const std::string &value);
+    void setBelAttr(IdStringList bel, IdString key, const std::string &value);
 
     void setLutK(int K);
     void setDelayScaling(double scale, double offset);
 
-    void addCellTimingClock(IdString cell, IdString port);
+    void addCellTimingClock(IdStringList cell, IdString port);
-    void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
+    void addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay);
-    void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
+    void addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
-    void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
+    void addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq);
 
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.
@@ -189,8 +192,8 @@ struct Arch : BaseCtx
     int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; }
     char getNameDelimiter() const { return '/'; }
 
-    BelId getBelByName(IdString name) const;
+    BelId getBelByName(IdStringList name) const;
-    IdString getBelName(BelId bel) const;
+    IdStringList getBelName(BelId bel) const;
     Loc getBelLocation(BelId bel) const;
     BelId getBelByLocation(Loc loc) const;
     const std::vector<BelId> &getBelsByTile(int x, int y) const;
@@ -208,8 +211,8 @@ struct Arch : BaseCtx
     PortType getBelPinType(BelId bel, IdString pin) const;
     std::vector<IdString> getBelPins(BelId bel) const;
 
-    WireId getWireByName(IdString name) const;
+    WireId getWireByName(IdStringList name) const;
-    IdString getWireName(WireId wire) const;
+    IdStringList getWireName(WireId wire) const;
     IdString getWireType(WireId wire) const;
     const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
     uint32_t getWireChecksum(WireId wire) const;
@@ -223,8 +226,8 @@ struct Arch : BaseCtx
     const std::vector<WireId> &getWires() const;
     const std::vector<BelPin> &getWireBelPins(WireId wire) const;
 
-    PipId getPipByName(IdString name) const;
+    PipId getPipByName(IdStringList name) const;
-    IdString getPipName(PipId pip) const;
+    IdStringList getPipName(PipId pip) const;
     IdString getPipType(PipId pip) const;
     const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
     uint32_t getPipChecksum(PipId pip) const;
@@ -242,8 +245,8 @@ struct Arch : BaseCtx
     const std::vector<PipId> &getPipsDownhill(WireId wire) const;
     const std::vector<PipId> &getPipsUphill(WireId wire) const;
 
-    GroupId getGroupByName(IdString name) const;
+    GroupId getGroupByName(IdStringList name) const;
-    IdString getGroupName(GroupId group) const;
+    IdStringList getGroupName(GroupId group) const;
     std::vector<GroupId> getGroups() const;
     const std::vector<BelId> &getGroupBels(GroupId group) const;
     const std::vector<WireId> &getGroupWires(GroupId group) const;

generic/arch_pybindings.cc

@@ -35,6 +35,7 @@ template <> struct string_converter<const IdString &>
 
     std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); }
 };
+
 } // namespace PythonConversion
 
 void arch_wrap_python(py::module &m)
@@ -152,37 +153,37 @@ void arch_wrap_python(py::module &m)
                     pass_through<float>>::def_wrap(ctx_cls, "addClock");
 
     // Generic arch construction API
-    fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdString>,
+    fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdStringList>,
                     conv_from_str<IdString>, pass_through<int>, pass_through<int>>::def_wrap(ctx_cls, "addWire",
                                                                                              "name"_a, "type"_a, "x"_a,
                                                                                              "y"_a);
-    fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdString>,
+    fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
+                    conv_from_str<IdString>, conv_from_str<IdStringList>, conv_from_str<IdStringList>,
-                    pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a,
+                    pass_through<DelayInfo>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a,
-                                                 "delay"_a, "loc"_a);
+                                                                          "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
 
-    fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>,
+    fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
                     conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
                                                                                               "name"_a, "type"_a,
                                                                                               "loc"_a, "gb"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdString>,
+    fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
+                    conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
-                                                                                "name"_a, "wire"_a);
+                                                                                    "name"_a, "wire"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdString>,
+    fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
+                    conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
-                                                                                "name"_a, "wire"_a);
+                                                                                    "name"_a, "wire"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdString>,
+    fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout", "bel"_a,
+                    conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInout", "bel"_a,
-                                                                                "name"_a, "wire"_a);
+                                                                                    "name"_a, "wire"_a);
 
-    fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdString>,
+    fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
+                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdString>,
+    fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
+                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdString>,
+    fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
+                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdString>,
+    fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a);
+                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a);
 
     fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
                     pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (py::arg("decal"), "graphic"));
@@ -211,16 +212,17 @@ void arch_wrap_python(py::module &m)
                     pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", "scale"_a, "offset"_a);
 
     fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock,
-                    conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock", "cell"_a,
+                    conv_from_str<IdStringList>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock",
-                                                                                "port"_a);
+                                                                                    "cell"_a, "port"_a);
     fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay,
-                    conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
+                    conv_from_str<IdStringList>, conv_from_str<IdString>, conv_from_str<IdString>,
                     pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay", "cell"_a, "fromPort"_a,
                                                        "toPort"_a, "delay"_a);
     fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold,
-                    conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
+                    conv_from_str<IdStringList>, conv_from_str<IdString>, conv_from_str<IdString>,
-                    pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold", "cell"_a, "port"_a, "clock"_a,
+                    pass_through<DelayInfo>, pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold",
-                                                       "setup"_a, "hold"_a);
+                                                                                "cell"_a, "port"_a, "clock"_a,
+                                                                                "setup"_a, "hold"_a);
     fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut,
                     conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
                     pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut", "cell"_a, "port"_a,

generic/archdefs.h

@@ -46,11 +46,11 @@ struct DelayInfo
     }
 };
 
-typedef IdString BelId;
+typedef IdStringList BelId;
-typedef IdString WireId;
+typedef IdStringList WireId;
-typedef IdString PipId;
+typedef IdStringList PipId;
-typedef IdString GroupId;
+typedef IdStringList GroupId;
-typedef IdString DecalId;
+typedef IdStringList DecalId;
 typedef IdString BelBucketId;
 
 struct ArchNetInfo