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Merge pull request #702 from YosysHQ/gatecat/interchange-fix-bb

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interchange: Fix bounding box computation
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gatecat 2021-05-11 13:59:09 +01:00 committed by GitHub
commit 7e3bb72049
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2 changed files with 3 additions and 3 deletions
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2
common/router2.cc
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@ -175,7 +175,7 @@ struct Router2
nets.at(i).bb.x0 = std::min(nets.at(i).bb.x0, ad.bb.x0);
nets.at(i).bb.x1 = std::max(nets.at(i).bb.x1, ad.bb.x1);
nets.at(i).bb.y0 = std::min(nets.at(i).bb.y0, ad.bb.y0);
nets.at(i).bb.y1 = std::max(nets.at(i).bb.x1, ad.bb.y1);
nets.at(i).bb.y1 = std::max(nets.at(i).bb.y1, ad.bb.y1);
}
// Add location to centroid sum
Loc usr_loc = ctx->getBelLocation(usr.cell->bel);

4
fpga_interchange/arch.cc
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@ -733,11 +733,12 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;
int x0 = 0, x1 = 0, y0 = 0, y1 = 0;
int src_x, src_y;
get_tile_x_y(src_tile, &src_x, &src_y);
int x0 = src_x, x1 = src_x, y0 = src_y, y1 = src_y;
int dst_x, dst_y;
get_tile_x_y(dst_tile, &dst_x, &dst_y);
@ -748,7 +749,6 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
y1 = std::max(y1, y);
};
expand(src_x, src_y);
expand(dst_x, dst_y);
if (source_locs.count(src))