Precompute pips too
This commit is contained in:
Eddie Hung
parent
ca7eef26ac
commit
7e693ff27d
53
xc7/arch.cc
53
xc7/arch.cc
@ -35,7 +35,7 @@ NEXTPNR_NAMESPACE_BEGIN
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std::unique_ptr<const TorcInfo> torc_info;
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TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string &inPackageName)
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: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), segments(ddb->getSegments()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_z(construct_bel_to_z(sites, num_bels, site_index_to_type)), wire_to_tilewire(construct_wire_to_tilewire(segments, tiles)), num_wires(wire_to_tilewire.size())
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: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), segments(ddb->getSegments()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_z(construct_bel_to_z(sites, num_bels, site_index_to_type)), wire_to_tilewire(construct_wire_to_tilewire(segments, tiles)), num_wires(wire_to_tilewire.size()), pip_to_arc(construct_pip_to_arc(wire_to_tilewire, *ddb, wire_to_pips_uphill, wire_to_pips_downhill)), num_pips(pip_to_arc.size())
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{
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}
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std::vector<SiteIndex> TorcInfo::construct_bel_to_site_index(Arch* ctx, const Sites &sites)
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@ -125,6 +125,55 @@ std::vector<Tilewire> TorcInfo::construct_wire_to_tilewire(const Segments& segme
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return wire_to_tilewire;
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}
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std::vector<Arc> TorcInfo::construct_pip_to_arc(const std::vector<Tilewire>& wire_to_tilewire, const DDB& ddb, std::vector<std::vector<int>> &wire_to_pips_uphill, std::vector<std::vector<int>> &wire_to_pips_downhill)
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{
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std::vector<Arc> pip_to_arc;
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wire_to_pips_downhill.resize(wire_to_tilewire.size());
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auto arc_hash = [](const Arc& arc) {
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size_t seed = 0;
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boost::hash_combine(seed, hash_value(arc.getSourceTilewire()));
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boost::hash_combine(seed, hash_value(arc.getSinkTilewire()));
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return seed;
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};
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std::unordered_map<Arc, int, decltype(arc_hash)> arc_to_pip(0, arc_hash);
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ArcVector arcs;
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for (auto i = 0u; i < wire_to_tilewire.size(); ++i) {
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const auto &tw = wire_to_tilewire[i];
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if (tw.isUndefined()) continue;
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arcs.clear();
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const_cast<DDB&>(ddb).expandSegmentSinks(tw, arcs);
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auto index = pip_to_arc.size();
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pip_to_arc.insert(pip_to_arc.end(), arcs.begin(), arcs.end());
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auto &pips = wire_to_pips_downhill[i];
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pips.reserve(arcs.size());
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for (const auto& a : arcs) {
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pips.push_back(index);
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arc_to_pip.emplace(a, index);
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++index;
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}
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}
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pip_to_arc.shrink_to_fit();
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wire_to_pips_uphill.resize(wire_to_tilewire.size());
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for (auto i = 0u; i < wire_to_tilewire.size(); ++i) {
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const auto &tw = wire_to_tilewire[i];
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if (tw.isUndefined()) continue;
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arcs.clear();
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const_cast<DDB&>(ddb).expandSegmentSinks(tw, arcs);
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auto &pips = wire_to_pips_uphill[i];
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pips.reserve(arcs.size());
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for (const auto& a : arcs)
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pips.push_back(arc_to_pip.at(a));
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}
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return pip_to_arc;
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}
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// -----------------------------------------------------------------------
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@ -160,7 +209,7 @@ Arch::Arch(ArchArgs args) : args(args)
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//bel_carry.resize(chip_info->num_bels);
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bel_to_cell.resize(torc_info->num_bels);
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wire_to_net.resize(torc_info->num_wires);
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//pip_to_net.resize(chip_info->num_pips);
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pip_to_net.resize(torc_info->num_pips);
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//switches_locked.resize(chip_info->num_switches);
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}
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126
xc7/arch.h
126
xc7/arch.h
@ -252,7 +252,7 @@ struct TorcInfo {
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}
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std::string wire_to_name(int32_t index) const
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{
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const auto tw = wire_to_tilewire[index];
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const auto &tw = wire_to_tilewire[index];
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ExtendedWireInfo ewi(*ddb, tw);
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std::stringstream ss;
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ss << ewi.mTileName << "/" << ewi.mWireName;
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@ -260,9 +260,16 @@ struct TorcInfo {
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}
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int32_t tilewire_to_wire(const Tilewire &tw) const
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{
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const auto& segment = segments.getTilewireSegment(tw);
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const auto &segment = segments.getTilewireSegment(tw);
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return segment.getCompactSegmentIndex();
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}
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int32_t pip_to_wire(int32_t index) const
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{
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const auto &arc = pip_to_arc[index];
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const auto &segment = segments.getTilewireSegment(arc.getSourceTilewire());
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return segment.getCompactSegmentIndex();
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}
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const std::vector<SiteIndex> bel_to_site_index;
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const int num_bels;
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@ -270,12 +277,18 @@ struct TorcInfo {
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const std::vector<int8_t> bel_to_z;
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const std::vector<Tilewire> wire_to_tilewire;
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const int num_wires;
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std::vector<std::vector<int>> wire_to_pips_uphill;
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std::vector<std::vector<int>> wire_to_pips_downhill;
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const std::vector<Arc> pip_to_arc;
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const int num_pips;
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private:
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static std::vector<SiteIndex> construct_bel_to_site_index(Arch *ctx, const Sites &sites);
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static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites);
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static std::vector<int8_t> construct_bel_to_z(const Sites &sites, const int num_bels, const std::vector<IdString> &site_index_to_type);
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static std::vector<Tilewire> construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles);
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static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire>& wire_to_tilewire, const DDB& ddb, std::vector<std::vector<int>> &wire_to_pips_uphill, std::vector<std::vector<int>> &wire_to_pips_downhill);
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};
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extern std::unique_ptr<const TorcInfo> torc_info;
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@ -435,11 +448,11 @@ struct Arch : BaseCtx
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mutable std::unordered_map<IdString, int> pip_by_name;
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mutable std::unordered_map<Loc, BelId> bel_by_loc;
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std::vector<bool> bel_carry;
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//std::vector<bool> bel_carry;
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std::vector<CellInfo *> bel_to_cell;
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std::vector<NetInfo *> wire_to_net;
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std::vector<NetInfo *> pip_to_net;
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std::vector<NetInfo *> switches_locked;
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//std::vector<NetInfo *> switches_locked;
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ArchArgs args;
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Arch(ArchArgs args);
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@ -533,7 +546,7 @@ struct Arch : BaseCtx
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Loc getBelLocation(BelId bel) const
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{
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auto &tile_info = torc_info->bel_to_tile_info(bel.index);
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const auto &tile_info = torc_info->bel_to_tile_info(bel.index);
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Loc loc;
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loc.x = tile_info.getCol();
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@ -591,11 +604,11 @@ struct Arch : BaseCtx
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auto it = net_wires.find(wire);
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NPNR_ASSERT(it != net_wires.end());
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//auto pip = it->second.pip;
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//if (pip != PipId()) {
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// pip_to_net[pip.index] = nullptr;
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// switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
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//}
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auto pip = it->second.pip;
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if (pip != PipId()) {
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pip_to_net[pip.index] = nullptr;
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//switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
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}
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net_wires.erase(it);
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wire_to_net[wire.index] = nullptr;
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@ -640,6 +653,7 @@ struct Arch : BaseCtx
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//NPNR_ASSERT(wire != WireId());
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//range.b.ptr = chip_info->wire_data[wire.index].bel_pins.get();
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//range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bel_pins;
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throw;
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return range;
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}
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@ -659,17 +673,16 @@ struct Arch : BaseCtx
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{
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip_to_net[pip.index] == nullptr);
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NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == nullptr);
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//NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == nullptr);
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pip_to_net[pip.index] = net;
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switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
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//switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
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WireId dst;
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//dst.index = chip_info->pip_data[pip.index].dst;
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WireId dst = getPipDstWire(pip);
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NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
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wire_to_net[dst.index] = net;
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//net->wires[dst].pip = pip;
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//net->wires[dst].strength = strength;
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net->wires[dst].pip = pip;
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net->wires[dst].strength = strength;
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refreshUiPip(pip);
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refreshUiWire(dst);
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}
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@ -678,16 +691,15 @@ struct Arch : BaseCtx
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{
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip_to_net[pip.index] != nullptr);
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NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != nullptr);
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//NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != nullptr);
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WireId dst;
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//dst.index = chip_info->pip_data[pip.index].dst;
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WireId dst = getPipDstWire(pip);
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NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
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wire_to_net[dst.index] = nullptr;
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pip_to_net[pip.index]->wires.erase(dst);
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pip_to_net[pip.index] = nullptr;
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switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
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//switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
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refreshUiPip(pip);
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refreshUiWire(dst);
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}
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@ -695,25 +707,26 @@ struct Arch : BaseCtx
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bool checkPipAvail(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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auto &pi = chip_info->pip_data[pip.index];
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auto &si = chip_info->bits_info->switches[pi.switch_index];
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//auto &pi = chip_info->pip_data[pip.index];
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//auto &si = chip_info->bits_info->switches[pi.switch_index];
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if (switches_locked[pi.switch_index] != nullptr)
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return false;
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//if (switches_locked[pi.switch_index] != nullptr)
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// return false;
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if (pi.flags & PipInfoPOD::FLAG_ROUTETHRU) {
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NPNR_ASSERT(si.bel >= 0);
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if (bel_to_cell[si.bel] != nullptr)
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return false;
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}
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//if (pi.flags & PipInfoPOD::FLAG_ROUTETHRU) {
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// NPNR_ASSERT(si.bel >= 0);
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// if (bel_to_cell[si.bel] != nullptr)
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// return false;
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//}
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if (pi.flags & PipInfoPOD::FLAG_NOCARRY) {
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NPNR_ASSERT(si.bel >= 0);
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if (bel_carry[si.bel])
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return false;
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}
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//if (pi.flags & PipInfoPOD::FLAG_NOCARRY) {
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// NPNR_ASSERT(si.bel >= 0);
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// if (bel_carry[si.bel])
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// return false;
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//}
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return true;
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//return true;
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return getConflictingPipNet(pip);
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}
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NetInfo *getBoundPipNet(PipId pip) const
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@ -725,22 +738,27 @@ struct Arch : BaseCtx
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NetInfo *getConflictingPipNet(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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return switches_locked[chip_info->pip_data[pip.index].switch_index];
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//return switches_locked[chip_info->pip_data[pip.index].switch_index];
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return pip_to_net[pip.index];
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}
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AllPipRange getPips() const
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{
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AllPipRange range;
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range.b.cursor = 0;
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range.e.cursor = chip_info->num_pips;
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range.e.cursor = torc_info->num_pips;
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return range;
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}
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Loc getPipLocation(PipId pip) const
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{
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const auto &arc = torc_info->pip_to_arc[pip.index];
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const auto &tw = arc.getSourceTilewire();
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const auto &tile_info = torc_info->tiles.getTileInfo(tw.getTileIndex());
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Loc loc;
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loc.x = chip_info->pip_data[pip.index].x;
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loc.y = chip_info->pip_data[pip.index].y;
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loc.x = tile_info.getCol();
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loc.y = tile_info.getRow();
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loc.z = 0;
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return loc;
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}
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@ -755,7 +773,11 @@ struct Arch : BaseCtx
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{
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WireId wire;
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NPNR_ASSERT(pip != PipId());
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//wire.index = chip_info->pip_data[pip.index].src;
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const auto &arc = torc_info->pip_to_arc[pip.index];
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const auto &tw = arc.getSourceTilewire();
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wire.index = torc_info->tilewire_to_wire(tw);
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return wire;
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}
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@ -763,7 +785,11 @@ struct Arch : BaseCtx
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{
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WireId wire;
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NPNR_ASSERT(pip != PipId());
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//wire.index = chip_info->pip_data[pip.index].dst;
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const auto &arc = torc_info->pip_to_arc[pip.index];
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const auto &tw = arc.getSinkTilewire();
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wire.index = torc_info->tilewire_to_wire(tw);
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return wire;
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}
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@ -771,10 +797,10 @@ struct Arch : BaseCtx
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{
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DelayInfo delay;
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NPNR_ASSERT(pip != PipId());
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if (fast_part)
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delay.delay = chip_info->pip_data[pip.index].fast_delay;
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else
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delay.delay = chip_info->pip_data[pip.index].slow_delay;
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//if (fast_part)
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// delay.delay = chip_info->pip_data[pip.index].fast_delay;
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//else
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// delay.delay = chip_info->pip_data[pip.index].slow_delay;
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return delay;
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}
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@ -782,8 +808,9 @@ struct Arch : BaseCtx
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{
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PipRange range;
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NPNR_ASSERT(wire != WireId());
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//range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
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//range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
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const auto &pips = torc_info->wire_to_pips_downhill[wire.index];
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range.b.cursor = pips.data();
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range.e.cursor = range.b.cursor + pips.size();
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return range;
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}
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@ -791,8 +818,9 @@ struct Arch : BaseCtx
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{
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PipRange range;
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NPNR_ASSERT(wire != WireId());
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//range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
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//range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
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const auto &pips = torc_info->wire_to_pips_uphill[wire.index];
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range.b.cursor = pips.data();
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range.e.cursor = range.b.cursor + pips.size();
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return range;
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}
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