Getting rid of users of old IdString API

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-18 16:08:19 +02:00
parent 0dd185a141
commit 7ef4d0726b
6 changed files with 50 additions and 48 deletions

View File

@ -58,7 +58,7 @@ void print_utilisation(const Context *ctx)
// Sort by Bel type // Sort by Bel type
std::map<BelType, int> used_types; std::map<BelType, int> used_types;
for (auto cell : ctx->cells) { for (auto cell : ctx->cells) {
used_types[belTypeFromId(cell.second->type)]++; used_types[ctx->belTypeFromId(cell.second->type)]++;
} }
std::map<BelType, int> available_types; std::map<BelType, int> available_types;
for (auto bel : ctx->getBels()) { for (auto bel : ctx->getBels()) {
@ -66,7 +66,7 @@ void print_utilisation(const Context *ctx)
} }
log("\nDesign utilisation:\n"); log("\nDesign utilisation:\n");
for (auto type : available_types) { for (auto type : available_types) {
log("\t%20s: %5d/%5d\n", belTypeToId(type.first).c_str(), log("\t%20s: %5d/%5d\n", ctx->belTypeToId(type.first).c_str(),
get_or_default(used_types, type.first, 0), type.second); get_or_default(used_types, type.first, 0), type.second);
} }
} }

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@ -84,7 +84,7 @@ static void place_initial(Context *ctx, CellInfo *cell, rnd_state &rnd)
ctx->unbindBel(cell->bel); ctx->unbindBel(cell->bel);
cell->bel = BelId(); cell->bel = BelId();
} }
BelType targetType = belTypeFromId(cell->type); BelType targetType = ctx->belTypeFromId(cell->type);
for (auto bel : ctx->getBels()) { for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) == targetType && if (ctx->getBelType(bel) == targetType &&
isValidBelForCell(ctx, cell, bel)) { isValidBelForCell(ctx, cell, bel)) {
@ -140,7 +140,7 @@ struct SAState
}; };
// Get the total estimated wirelength for a net // Get the total estimated wirelength for a net
static float get_wirelength(Arch *chip, NetInfo *net) static float get_wirelength(Context *ctx, NetInfo *net)
{ {
float wirelength = 0; float wirelength = 0;
int driver_x = 0, driver_y = 0; int driver_x = 0, driver_y = 0;
@ -151,9 +151,9 @@ static float get_wirelength(Arch *chip, NetInfo *net)
if (driver_cell->bel == BelId()) if (driver_cell->bel == BelId())
return 0; return 0;
consider_driver = consider_driver =
chip->estimatePosition(driver_cell->bel, driver_x, driver_y); ctx->estimatePosition(driver_cell->bel, driver_x, driver_y);
WireId drv_wire = chip->getWireBelPin(driver_cell->bel, WireId drv_wire = ctx->getWireBelPin(driver_cell->bel,
portPinFromId(net->driver.port)); ctx->portPinFromId(net->driver.port));
if (!consider_driver) if (!consider_driver)
return 0; return 0;
for (auto load : net->users) { for (auto load : net->users) {
@ -162,12 +162,12 @@ static float get_wirelength(Arch *chip, NetInfo *net)
CellInfo *load_cell = load.cell; CellInfo *load_cell = load.cell;
if (load_cell->bel == BelId()) if (load_cell->bel == BelId())
continue; continue;
// chip->estimatePosition(load_cell->bel, load_x, load_y); // ctx->estimatePosition(load_cell->bel, load_x, load_y);
WireId user_wire = WireId user_wire = ctx->getWireBelPin(load_cell->bel,
chip->getWireBelPin(load_cell->bel, portPinFromId(load.port)); ctx->portPinFromId(load.port));
// wirelength += std::abs(load_x - driver_x) + std::abs(load_y - // wirelength += std::abs(load_x - driver_x) + std::abs(load_y -
// driver_y); // driver_y);
wirelength += chip->estimateDelay(drv_wire, user_wire); wirelength += ctx->estimateDelay(drv_wire, user_wire);
} }
return wirelength; return wirelength;
} }
@ -262,7 +262,7 @@ swap_fail:
BelId random_bel_for_cell(Context *ctx, CellInfo *cell, SAState &state, BelId random_bel_for_cell(Context *ctx, CellInfo *cell, SAState &state,
rnd_state &rnd) rnd_state &rnd)
{ {
BelType targetType = belTypeFromId(cell->type); BelType targetType = ctx->belTypeFromId(cell->type);
int x = 0, y = 0; int x = 0, y = 0;
ctx->estimatePosition(cell->bel, x, y); ctx->estimatePosition(cell->bel, x, y);
while (true) { while (true) {
@ -305,10 +305,10 @@ void place_design_sa(Context *ctx, int seed)
} }
BelType bel_type = ctx->getBelType(bel); BelType bel_type = ctx->getBelType(bel);
if (bel_type != belTypeFromId(cell->type)) { if (bel_type != ctx->belTypeFromId(cell->type)) {
log_error("Bel \'%s\' of type \'%s\' does not match cell " log_error("Bel \'%s\' of type \'%s\' does not match cell "
"\'%s\' of type \'%s\'", "\'%s\' of type \'%s\'",
loc_name.c_str(), belTypeToId(bel_type).c_str(), loc_name.c_str(), ctx->belTypeToId(bel_type).c_str(),
cell->name.c_str(), cell->type.c_str()); cell->name.c_str(), cell->type.c_str());
} }

View File

@ -93,7 +93,8 @@ struct Router
if (driver_port_it != net_info->driver.cell->pins.end()) if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second; driver_port = driver_port_it->second;
auto src_wire = ctx->getWireBelPin(src_bel, portPinFromId(driver_port)); auto src_wire =
ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
if (src_wire == WireId()) if (src_wire == WireId())
log_error("No wire found for port %s (pin %s) on source cell %s " log_error("No wire found for port %s (pin %s) on source cell %s "
@ -134,7 +135,7 @@ struct Router
user_port = user_port_it->second; user_port = user_port_it->second;
auto dst_wire = auto dst_wire =
ctx->getWireBelPin(dst_bel, portPinFromId(user_port)); ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
if (dst_wire == WireId()) if (dst_wire == WireId())
log_error("No wire found for port %s (pin %s) on destination " log_error("No wire found for port %s (pin %s) on destination "
@ -335,7 +336,8 @@ bool route_design(Context *ctx, bool verbose)
if (driver_port_it != net_info->driver.cell->pins.end()) if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second; driver_port = driver_port_it->second;
auto src_wire = ctx->getWireBelPin(src_bel, portPinFromId(driver_port)); auto src_wire =
ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
if (src_wire == WireId()) if (src_wire == WireId())
continue; continue;
@ -354,7 +356,7 @@ bool route_design(Context *ctx, bool verbose)
user_port = user_port_it->second; user_port = user_port_it->second;
auto dst_wire = auto dst_wire =
ctx->getWireBelPin(dst_bel, portPinFromId(user_port)); ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
if (dst_wire == WireId()) if (dst_wire == WireId())
continue; continue;

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@ -47,12 +47,6 @@ struct DelayInfo
typedef IdString BelType; typedef IdString BelType;
typedef IdString PortPin; typedef IdString PortPin;
static inline IdString belTypeToId(BelType type) { return type; }
static inline IdString portPinToId(PortPin type) { return type; }
static inline BelType belTypeFromId(IdString id) { return id; }
static inline PortPin portPinFromId(IdString id) { return id; }
typedef IdString BelId; typedef IdString BelId;
typedef IdString WireId; typedef IdString WireId;
typedef IdString PipId; typedef IdString PipId;
@ -76,6 +70,12 @@ struct Arch
virtual IdString id(const std::string &s) const { abort(); } virtual IdString id(const std::string &s) const { abort(); }
virtual IdString id(const char *s) const { abort(); } virtual IdString id(const char *s) const { abort(); }
IdString belTypeToId(BelType type) const { return type; }
IdString portPinToId(PortPin type) const { return type; }
BelType belTypeFromId(IdString id) const { return id; }
PortPin portPinFromId(IdString id) const { return id; }
BelId getBelByName(IdString name) const; BelId getBelByName(IdString name) const;
IdString getBelName(BelId bel) const; IdString getBelName(BelId bel) const;
void bindBel(BelId bel, IdString cell); void bindBel(BelId bel, IdString cell);

View File

@ -26,28 +26,28 @@ NEXTPNR_NAMESPACE_BEGIN
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
IdString belTypeToId(BelType type) IdString Arch::belTypeToId(BelType type) const
{ {
if (type == TYPE_ICESTORM_LC) if (type == TYPE_ICESTORM_LC)
return "ICESTORM_LC"; return id("ICESTORM_LC");
if (type == TYPE_ICESTORM_RAM) if (type == TYPE_ICESTORM_RAM)
return "ICESTORM_RAM"; return id("ICESTORM_RAM");
if (type == TYPE_SB_IO) if (type == TYPE_SB_IO)
return "SB_IO"; return id("SB_IO");
if (type == TYPE_SB_GB) if (type == TYPE_SB_GB)
return "SB_GB"; return id("SB_GB");
return IdString(); return IdString();
} }
BelType belTypeFromId(IdString id) BelType Arch::belTypeFromId(IdString type) const
{ {
if (id == "ICESTORM_LC") if (type == id("ICESTORM_LC"))
return TYPE_ICESTORM_LC; return TYPE_ICESTORM_LC;
if (id == "ICESTORM_RAM") if (type == id("ICESTORM_RAM"))
return TYPE_ICESTORM_RAM; return TYPE_ICESTORM_RAM;
if (id == "SB_IO") if (type == id("SB_IO"))
return TYPE_SB_IO; return TYPE_SB_IO;
if (id == "SB_GB") if (type == id("SB_GB"))
return TYPE_SB_GB; return TYPE_SB_GB;
return TYPE_NONE; return TYPE_NONE;
} }
@ -61,7 +61,7 @@ void IdString::initialize_arch(const Context *ctx)
#undef X #undef X
} }
IdString portPinToId(PortPin type) IdString Arch::portPinToId(PortPin type) const
{ {
IdString ret; IdString ret;
if (type > 0 && type < PIN_MAXIDX) if (type > 0 && type < PIN_MAXIDX)
@ -69,10 +69,10 @@ IdString portPinToId(PortPin type)
return ret; return ret;
} }
PortPin portPinFromId(IdString id) PortPin Arch::portPinFromId(IdString type) const
{ {
if (id.index > 0 && id.index < PIN_MAXIDX) if (type.index > 0 && type.index < PIN_MAXIDX)
return PortPin(id.index); return PortPin(type.index);
return PIN_NONE; return PIN_NONE;
} }
@ -163,7 +163,7 @@ BelId Arch::getBelByName(IdString name) const
if (bel_by_name.empty()) { if (bel_by_name.empty()) {
for (int i = 0; i < chip_info->num_bels; i++) for (int i = 0; i < chip_info->num_bels; i++)
bel_by_name[chip_info->bel_data[i].name.get()] = i; bel_by_name[id(chip_info->bel_data[i].name.get())] = i;
} }
auto it = bel_by_name.find(name); auto it = bel_by_name.find(name);
@ -220,7 +220,7 @@ WireId Arch::getWireByName(IdString name) const
if (wire_by_name.empty()) { if (wire_by_name.empty()) {
for (int i = 0; i < chip_info->num_wires; i++) for (int i = 0; i < chip_info->num_wires; i++)
wire_by_name[chip_info->wire_data[i].name.get()] = i; wire_by_name[id(chip_info->wire_data[i].name.get())] = i;
} }
auto it = wire_by_name.find(name); auto it = wire_by_name.find(name);
@ -266,8 +266,8 @@ IdString Arch::getPipName(PipId pip) const
chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get(); chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
std::replace(dst_name.begin(), dst_name.end(), '/', '.'); std::replace(dst_name.begin(), dst_name.end(), '/', '.');
return "X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" +
".->." + dst_name; src_name + ".->." + dst_name);
} }
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------

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@ -55,9 +55,6 @@ enum BelType : int32_t
TYPE_SB_GB TYPE_SB_GB
}; };
IdString belTypeToId(BelType type);
BelType belTypeFromId(IdString id);
enum PortPin : int32_t enum PortPin : int32_t
{ {
PIN_NONE, PIN_NONE,
@ -67,9 +64,6 @@ enum PortPin : int32_t
PIN_MAXIDX PIN_MAXIDX
}; };
IdString portPinToId(PortPin type);
PortPin portPinFromId(IdString id);
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
/**** Everything in this section must be kept in sync with chipdb.py ****/ /**** Everything in this section must be kept in sync with chipdb.py ****/
@ -480,6 +474,12 @@ struct Arch
virtual IdString id(const std::string &s) const { abort(); } virtual IdString id(const std::string &s) const { abort(); }
virtual IdString id(const char *s) const { abort(); } virtual IdString id(const char *s) const { abort(); }
IdString belTypeToId(BelType type) const;
BelType belTypeFromId(IdString id) const;
IdString portPinToId(PortPin type) const;
PortPin portPinFromId(IdString id) const;
// ------------------------------------------------- // -------------------------------------------------
BelId getBelByName(IdString name) const; BelId getBelByName(IdString name) const;