ODDR2
This commit is contained in:
Marcin Kościelnicki
parent
5db6939a8e
commit
7f437cbf62
@ -127,9 +127,32 @@ std::unique_ptr<CellInfo> create_leuctra_cell(Context *ctx, IdString type, std::
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add_port(ctx, new_cell.get(), "FABRICOUT", PORT_OUT);
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} else if (type == ctx->id("OLOGIC2")) {
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add_port(ctx, new_cell.get(), "D1", PORT_IN);
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add_port(ctx, new_cell.get(), "D2", PORT_IN);
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add_port(ctx, new_cell.get(), "D3", PORT_IN);
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add_port(ctx, new_cell.get(), "D4", PORT_IN);
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add_port(ctx, new_cell.get(), "OQ", PORT_OUT);
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add_port(ctx, new_cell.get(), "T1", PORT_IN);
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add_port(ctx, new_cell.get(), "T2", PORT_IN);
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add_port(ctx, new_cell.get(), "T3", PORT_IN);
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add_port(ctx, new_cell.get(), "T4", PORT_IN);
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add_port(ctx, new_cell.get(), "TQ", PORT_OUT);
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add_port(ctx, new_cell.get(), "SR", PORT_IN);
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add_port(ctx, new_cell.get(), "REV", PORT_IN);
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add_port(ctx, new_cell.get(), "OCE", PORT_IN);
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add_port(ctx, new_cell.get(), "TCE", PORT_IN);
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add_port(ctx, new_cell.get(), "IOCE", PORT_IN);
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add_port(ctx, new_cell.get(), "TRAIN", PORT_IN);
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add_port(ctx, new_cell.get(), "CLK0", PORT_IN);
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add_port(ctx, new_cell.get(), "CLK1", PORT_IN);
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add_port(ctx, new_cell.get(), "CLKDIV", PORT_IN);
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add_port(ctx, new_cell.get(), "SHIFTIN1", PORT_IN);
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add_port(ctx, new_cell.get(), "SHIFTIN2", PORT_IN);
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add_port(ctx, new_cell.get(), "SHIFTIN3", PORT_IN);
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add_port(ctx, new_cell.get(), "SHIFTIN4", PORT_IN);
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add_port(ctx, new_cell.get(), "SHIFTOUT1", PORT_OUT);
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add_port(ctx, new_cell.get(), "SHIFTOUT2", PORT_OUT);
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add_port(ctx, new_cell.get(), "SHIFTOUT3", PORT_OUT);
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add_port(ctx, new_cell.get(), "SHIFTOUT4", PORT_OUT);
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} else {
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log_error("unable to create Leuctra cell of type %s", type.c_str(ctx));
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}
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240
leuctra/pack.cc
240
leuctra/pack.cc
@ -355,19 +355,10 @@ class LeuctraPacker
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NetInfo *net_t = nullptr;
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if (port_t != IdString())
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net_t = ci->ports.at(port_t).net;
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connect_port(ctx, net_o, iobm, ctx->id("O"));
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if (kind == IOSTD_PSEUDO_DIFF) {
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// XXX
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NPNR_ASSERT_FALSE("PSEUDO DIFF OUTPUT");
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connect_port(ctx, net_o, iobs, ctx->id("O"));
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}
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disconnect_port(ctx, ci, port_o);
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if (net_t) {
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connect_port(ctx, net_t, iobm, ctx->id("T"));
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if (kind == IOSTD_PSEUDO_DIFF)
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connect_port(ctx, net_t, iobs, ctx->id("T"));
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if (net_o)
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disconnect_port(ctx, ci, port_o);
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if (net_t)
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disconnect_port(ctx, ci, port_t);
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}
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iobm->params[ctx->id("OSTANDARD")] = Property(iostd);
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if (iobs)
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iobs->params[ctx->id("OSTANDARD")] = Property(iostd);
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@ -397,14 +388,209 @@ class LeuctraPacker
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connect_ports(ctx, iobm, ctx->id("DIFFO_OUT"), iobs, ctx->id("DIFFO_IN"));
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iobs->params[ctx->id("OUTMUX")] = Property("0");
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}
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// OLOGIC handling.
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std::unique_ptr<CellInfo> ologic_cell =
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create_leuctra_cell(ctx, ctx->id("OLOGIC2"), ci->name.str(ctx) + "$ologic");
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new_cells.push_back(std::move(ologic_cell));
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CellInfo *ologic_m = new_cells.back().get();
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CellInfo *ologic_s;
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std::vector<CellInfo *> ologics{ologic_m};
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connect_ports(ctx, ologic_m, ctx->id("OQ"), iobm, ctx->id("O"));
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if (net_t)
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connect_ports(ctx, ologic_m, ctx->id("TQ"), iobm, ctx->id("T"));
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ologic_m->constr_parent = iobm;
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ologic_m->constr_spec = 2;
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iobm->constr_children.push_back(ologic_m);
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if (kind == IOSTD_PSEUDO_DIFF) {
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std::unique_ptr<CellInfo> ologic_s_cell =
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create_leuctra_cell(ctx, ctx->id("OLOGIC2"), ci->name.str(ctx) + "$ologic_s");
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new_cells.push_back(std::move(ologic_s_cell));
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ologic_s = new_cells.back().get();
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ologics.push_back(ologic_s);
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connect_ports(ctx, ologic_s, ctx->id("OQ"), iobs, ctx->id("O"));
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if (net_t)
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connect_ports(ctx, ologic_s, ctx->id("TQ"), iobs, ctx->id("T"));
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ologic_s->constr_parent = iobs;
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ologic_s->constr_spec = 2;
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iobs->constr_children.push_back(ologic_s);
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}
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CellInfo *oddr = net_driven_by(
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ctx, net_o, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("ODDR2"); }, ctx->id("Q"));
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if (oddr) {
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packed_cells.insert(oddr->name);
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CellInfo *oddr_t = nullptr;
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if (net_t) {
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oddr_t = net_driven_by(
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ctx, net_t, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("ODDR2"); }, ctx->id("Q"));
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if (!oddr_t)
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log_error("%s: an IO pad driven by ODDR2 with tristate requires the tri-state control to be driven by ODDR2 as well.\n", ci->name.c_str(ctx));
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}
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disconnect_port(ctx, oddr, ctx->id("Q"));
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NetInfo *d1 = oddr->ports[ctx->id("D0")].net;
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NetInfo *d2 = oddr->ports[ctx->id("D1")].net;
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NetInfo *c0 = nullptr, *c1 = nullptr;
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bool inv_c0, inv_c1;
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get_invertible_port(ctx, oddr, ctx->id("C0"), false, true, c0, inv_c0);
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get_invertible_port(ctx, oddr, ctx->id("C1"), false, true, c1, inv_c1);
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NetInfo *ce = oddr->ports[ctx->id("CE")].net;
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NetInfo *ce_t = nullptr;
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NetInfo *sr_t = nullptr;
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NetInfo *rev_t = nullptr;
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NetInfo *sr = nullptr;
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NetInfo *rev = nullptr;
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Property init(0, 1);
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Property init_t(0, 1);
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if (oddr->params.count(ctx->id("INIT")))
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init = oddr->params[ctx->id("INIT")];
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if (init.as_bool()) {
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sr = oddr->ports[ctx->id("S")].net;
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rev = oddr->ports[ctx->id("R")].net;
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} else {
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rev = oddr->ports[ctx->id("S")].net;
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sr = oddr->ports[ctx->id("R")].net;
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}
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disconnect_port(ctx, oddr, ctx->id("D0"));
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disconnect_port(ctx, oddr, ctx->id("D1"));
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disconnect_port(ctx, oddr, ctx->id("CE"));
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disconnect_port(ctx, oddr, ctx->id("S"));
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disconnect_port(ctx, oddr, ctx->id("R"));
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NetInfo *t1 = nullptr;
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NetInfo *t2 = nullptr;
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Property srtype("SYNC");
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if (oddr->params.count(ctx->id("SRTYPE")))
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srtype = oddr->params[ctx->id("SRTYPE")];
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Property srtype_t("SYNC");
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Property align("NONE");
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if (oddr->params.count(ctx->id("DDR_ALIGNMENT")))
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align = oddr->params[ctx->id("DDR_ALIGNMENT")];
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Property align_t("NONE");
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if (oddr_t) {
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packed_cells.insert(oddr_t->name);
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disconnect_port(ctx, oddr_t, ctx->id("Q"));
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t1 = oddr_t->ports[ctx->id("D0")].net;
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t2 = oddr_t->ports[ctx->id("D1")].net;
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NetInfo *c0_t = nullptr, *c1_t = nullptr;
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bool inv_c0_t, inv_c1_t;
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get_invertible_port(ctx, oddr_t, ctx->id("C0"), false, true, c0_t, inv_c0_t);
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get_invertible_port(ctx, oddr_t, ctx->id("C1"), false, true, c1_t, inv_c1_t);
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if (c0 != c0_t || c1 != c1_t || inv_c0 != inv_c0_t || inv_c1 != inv_c1_t)
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log_error("%s: mismatched clocking between O and T\n", ci->name.c_str(ctx));
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ce_t = oddr_t->ports[ctx->id("CE")].net;
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if (oddr_t->params.count(ctx->id("INIT")))
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init_t = oddr_t->params[ctx->id("INIT")];
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if (init_t.as_bool()) {
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sr_t = oddr_t->ports[ctx->id("S")].net;
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rev_t = oddr_t->ports[ctx->id("R")].net;
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} else {
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rev_t = oddr_t->ports[ctx->id("S")].net;
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sr_t = oddr_t->ports[ctx->id("R")].net;
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}
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disconnect_port(ctx, oddr_t, ctx->id("D0"));
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disconnect_port(ctx, oddr_t, ctx->id("D1"));
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disconnect_port(ctx, oddr_t, ctx->id("CE"));
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disconnect_port(ctx, oddr_t, ctx->id("S"));
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disconnect_port(ctx, oddr_t, ctx->id("R"));
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if (sr && sr_t && sr != sr_t)
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log_error("%s: mismatched SR port between O and T\n", ci->name.c_str(ctx));
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if (rev && rev_t && rev != rev_t)
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log_error("%s: mismatched REV port between O and T\n", ci->name.c_str(ctx));
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if (oddr_t->params.count(ctx->id("SRTYPE")))
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srtype_t = oddr_t->params[ctx->id("SRTYPE")];
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if (oddr_t->params.count(ctx->id("DDR_ALIGNMENT")))
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align_t = oddr_t->params[ctx->id("DDR_ALIGNMENT")];
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}
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for (auto ol: ologics) {
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ol->params[ctx->id("OUTFFTYPE")] = Property("DDR");
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ol->params[ctx->id("OMUX")] = Property("OUTFF");
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ol->params[ctx->id("SRTYPE_OQ")] = srtype;
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ol->params[ctx->id("DDR_ALIGNMENT")] = align;
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set_invertible_port(ctx, ol, ctx->id("CLK0"), c0, inv_c0, true, new_cells);
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set_invertible_port(ctx, ol, ctx->id("CLK1"), c1, inv_c1, true, new_cells);
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ol->params[ctx->id("D1USED")] = Property("0");
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ol->params[ctx->id("D2USED")] = Property("0");
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if (ce) {
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connect_port(ctx, ce, ol, ctx->id("OCE"));
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ol->params[ctx->id("OCEUSED")] = Property("0");
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}
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if (ce_t) {
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connect_port(ctx, ce_t, ol, ctx->id("TCE"));
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ol->params[ctx->id("TCEUSED")] = Property("0");
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}
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if (sr) {
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connect_port(ctx, sr, ol, ctx->id("SR"));
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ol->params[ctx->id("OSRUSED")] = Property("0");
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}
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if (sr_t) {
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if (!sr)
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connect_port(ctx, sr_t, ol, ctx->id("SR"));
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ol->params[ctx->id("TSRUSED")] = Property("0");
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}
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if (rev) {
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connect_port(ctx, rev, ol, ctx->id("REV"));
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ol->params[ctx->id("OREVUSED")] = Property("0");
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}
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if (rev_t) {
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if (!rev)
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connect_port(ctx, rev_t, ol, ctx->id("REV"));
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ol->params[ctx->id("TREVUSED")] = Property("0");
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}
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if (oddr_t) {
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ol->params[ctx->id("TFFTYPE")] = Property("DDR");
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ol->params[ctx->id("TMUX")] = Property("TFF");
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ol->params[ctx->id("T1USED")] = Property("0");
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ol->params[ctx->id("SRTYPE_TQ")] = srtype_t;
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ol->params[ctx->id("TDDR_ALIGNMENT")] = align_t;
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connect_port(ctx, t1, ol, ctx->id("T1"));
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connect_port(ctx, t2, ol, ctx->id("T2"));
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ol->params[ctx->id("SRINIT_TQ")] = init_t;
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}
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}
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ologic_m->params[ctx->id("SRINIT_OQ")] = init;
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connect_port(ctx, d1, ologic_m, ctx->id("D1"));
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connect_port(ctx, d2, ologic_m, ctx->id("D2"));
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if (ologic_s) {
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ologic_s->params[ctx->id("SRINIT_OQ")] = Property(!init.as_bool());
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set_invertible_port(ctx, ologic_s, ctx->id("D1"), d1, true, false, new_cells);
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set_invertible_port(ctx, ologic_s, ctx->id("D2"), d2, true, false, new_cells);
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}
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} else {
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// Plain logic passthru.
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for (auto ol: ologics) {
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ol->params[ctx->id("OMUX")] = Property("D1");
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ol->params[ctx->id("D1USED")] = Property("0");
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ol->params[ctx->id("O1USED")] = Property("0");
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if (net_t) {
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ol->params[ctx->id("TMUX")] = Property("T1");
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ol->params[ctx->id("T1USED")] = Property("0");
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connect_port(ctx, net_t, ol, ctx->id("T1"));
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}
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}
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connect_port(ctx, net_o, ologic_m, ctx->id("D1"));
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if (kind == IOSTD_PSEUDO_DIFF) {
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set_invertible_port(ctx, ologic_s, ctx->id("D1"), net_o, true, false, new_cells);
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}
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}
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}
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if (ci->params.count(ctx->id("PULLTYPE")))
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// XXX use the iobs contraint version?
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if (ci->params.count(ctx->id("PULLTYPE"))) {
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iobm->params[ctx->id("PULLTYPE")] = ci->params[ctx->id("PULLTYPE")];
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if (ci->params.count(ctx->id("SUSPEND")))
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if (iobs)
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iobs->params[ctx->id("PULLTYPE")] = ci->params[ctx->id("PULLTYPE")];
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}
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if (ci->params.count(ctx->id("SUSPEND"))) {
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iobm->params[ctx->id("SUSPEND")] = ci->params[ctx->id("SUSPEND")];
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if (ci->params.count(ctx->id("PRE_EMPHASIS")))
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if (iobs)
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iobs->params[ctx->id("SUSPEND")] = ci->params[ctx->id("SUSPEND")];
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}
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if (ci->params.count(ctx->id("PRE_EMPHASIS"))) {
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iobm->params[ctx->id("PRE_EMPHASIS")] = ci->params[ctx->id("PRE_EMPHASIS")];
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if (iobs)
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iobs->params[ctx->id("PRE_EMPHASIS")] = ci->params[ctx->id("PRE_EMPHASIS")];
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}
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auto loc_attr = ci->attrs.find(ctx->id("LOC"));
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if (loc_attr != ci->attrs.end()) {
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@ -457,6 +643,7 @@ class LeuctraPacker
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new_cells.push_back(std::move(ilogic));
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}
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#if 0
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NetInfo *net_o = ci->ports.at(ctx->id("O")).net;
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if (net_o != nullptr) {
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// Insert OLOGIC.
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@ -466,6 +653,7 @@ class LeuctraPacker
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new_cells.push_back(std::move(ologic));
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}
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#endif
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auto bel_attr = ci->attrs.find(ctx->id("BEL"));
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if (bel_attr != ci->attrs.end()) {
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BelId bel = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")].as_string()));
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@ -814,6 +1002,26 @@ class LeuctraPacker
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flush_cells();
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}
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// Remove leftover INVs.
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void clean_inv()
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{
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log_info("Removing unused INVs...\n");
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type == ctx->id("INV")) {
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NetInfo *net = ci->ports.at(ctx->id("O")).net;
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if (net->users.size() == 0) {
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disconnect_port(ctx, ci, ctx->id("O"));
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disconnect_port(ctx, ci, ctx->id("I"));
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packed_cells.insert(ci->name);
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}
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}
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}
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flush_cells();
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}
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// Convert LUTs to LEUCTRA_LCs.
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void pack_lut()
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{
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@ -994,7 +1202,7 @@ class LeuctraPacker
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pack_carry();
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pack_muxf8();
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pack_muxf7();
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// clean_inv();
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clean_inv();
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pack_lut();
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// pack_lc_ff();
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pack_misc();
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