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Import lutperm data

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This commit is contained in:
Miodrag Milanovic 2023-03-30 13:38:02 +02:00 committed by myrtle
parent 442142a47a
commit 7f8518d938
2 changed files with 6 additions and 2 deletions
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2
machxo2/arch.h
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@ -62,6 +62,8 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
int16_t tile_type;
int8_t pip_type;
int8_t padding;
int16_t lutperm_flags;
int16_t padding2;
});
NPNR_PACKED_STRUCT(struct PipLocatorPOD {

6
machxo2/facade_import.py
View File

@ -11,7 +11,7 @@ gfx_wire_names = list()
parser = argparse.ArgumentParser(description="import MachXO2 routing and bels from Project Trellis")
parser.add_argument("device", type=str, help="target device")
parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h (unused)")
parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
parser.add_argument("-L", "--libdir", type=str, action="append", help="extra Python library path")
args = parser.parse_args()
@ -268,6 +268,8 @@ def write_database(dev_name, chip, rg, endianness):
cls = arc.cls
bba.u8(arc.cls, "pip_type")
bba.u8(0, "padding")
bba.u16(arc.lutperm_flags, "lutperm_flags")
bba.u16(0, "padding2")
if len(t.wires) > 0:
for wire_idx in range(len(t.wires)):
@ -481,7 +483,7 @@ def main():
constids["PIO"] = constids["TRELLIS_IO"]
chip = pytrellis.Chip(dev_names[args.device])
rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=True)
rg = pytrellis.make_optimized_chipdb(chip, include_lutperm_pips=True, split_slice_mode=True)
max_row = chip.get_max_row()
max_col = chip.get_max_col()
process_pio_db(rg, args.device)