Add RFB/RAM context support for latest release
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@ -365,14 +365,20 @@ struct BitstreamJsonBackend
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log_error("Unknown mode %d for cell '%s'.\n", mode, cell->name.c_str(ctx));
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}
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add_config("mode", mode);
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add_config("context", str_or_default(cell->params, ctx->id("mem_ctxt"), ""));
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add_config("wck_edge", bool_or_default(cell->params, ctx->id("wck_edge"), false));
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close_instance();
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}
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void write_ram(CellInfo *cell) {
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open_instance(cell, "RAM");
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add_config("mcka_edge", bool_or_default(cell->params, ctx->id("mcka_edge"), false));
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add_config("mckb_edge", bool_or_default(cell->params, ctx->id("mckb_edge"), false));
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add_config("pcka_edge", bool_or_default(cell->params, ctx->id("pcka_edge"), false));
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add_config("pckb_edge", bool_or_default(cell->params, ctx->id("pckb_edge"), false));
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add_config("raw_config0", extract_bits_or_default(cell->params, ctx->id("raw_config0"), 4));
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add_config("raw_config1", extract_bits_or_default(cell->params, ctx->id("raw_config1"), 16));
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add_config("context", str_or_default(cell->params, ctx->id("mem_ctxt"), ""));
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close_instance();
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}
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@ -1044,6 +1044,10 @@ void NgUltraPacker::pack_rams(void)
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ci.disconnectPort(id_BCKC);
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ci.disconnectPort(id_BCKD);
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ci.disconnectPort(id_BCKR);
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for (auto &p : ci.ports) {
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if (p.second.type == PortType::PORT_IN)
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disconnect_if_gnd(&ci, p.first);
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}
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}
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}
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