From 7fd21226142b58c937f1bbfc8808edcac9156847 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 23 May 2024 12:18:32 +0200 Subject: [PATCH] Add RFB/RAM context support for latest release --- himbaechel/uarch/ng-ultra/bitstream.cc | 6 ++++++ himbaechel/uarch/ng-ultra/pack.cc | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/himbaechel/uarch/ng-ultra/bitstream.cc b/himbaechel/uarch/ng-ultra/bitstream.cc index 31f0ca8a..f288ac50 100644 --- a/himbaechel/uarch/ng-ultra/bitstream.cc +++ b/himbaechel/uarch/ng-ultra/bitstream.cc @@ -365,14 +365,20 @@ struct BitstreamJsonBackend log_error("Unknown mode %d for cell '%s'.\n", mode, cell->name.c_str(ctx)); } add_config("mode", mode); + add_config("context", str_or_default(cell->params, ctx->id("mem_ctxt"), "")); add_config("wck_edge", bool_or_default(cell->params, ctx->id("wck_edge"), false)); close_instance(); } void write_ram(CellInfo *cell) { open_instance(cell, "RAM"); + add_config("mcka_edge", bool_or_default(cell->params, ctx->id("mcka_edge"), false)); + add_config("mckb_edge", bool_or_default(cell->params, ctx->id("mckb_edge"), false)); + add_config("pcka_edge", bool_or_default(cell->params, ctx->id("pcka_edge"), false)); + add_config("pckb_edge", bool_or_default(cell->params, ctx->id("pckb_edge"), false)); add_config("raw_config0", extract_bits_or_default(cell->params, ctx->id("raw_config0"), 4)); add_config("raw_config1", extract_bits_or_default(cell->params, ctx->id("raw_config1"), 16)); + add_config("context", str_or_default(cell->params, ctx->id("mem_ctxt"), "")); close_instance(); } diff --git a/himbaechel/uarch/ng-ultra/pack.cc b/himbaechel/uarch/ng-ultra/pack.cc index b226ec23..86329dd0 100644 --- a/himbaechel/uarch/ng-ultra/pack.cc +++ b/himbaechel/uarch/ng-ultra/pack.cc @@ -1044,6 +1044,10 @@ void NgUltraPacker::pack_rams(void) ci.disconnectPort(id_BCKC); ci.disconnectPort(id_BCKD); ci.disconnectPort(id_BCKR); + for (auto &p : ci.ports) { + if (p.second.type == PortType::PORT_IN) + disconnect_if_gnd(&ci, p.first); + } } }