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Add more missing iCE40 gfx (LP/HX is complete now)

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-08-19 18:43:38 +02:00
parent 49d3857f97
commit 801f630983
3 changed files with 47 additions and 4 deletions
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46
ice40/arch.cc
View File

@ -730,12 +730,28 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
for (int i = 0; i < n; i++) for (int i = 0; i < n; i++)
gfxTileWire(ret, p[i].x, p[i].y, chip_info->width, chip_info->height, GfxTileWireId(p[i].index), style); gfxTileWire(ret, p[i].x, p[i].y, chip_info->width, chip_info->height, GfxTileWireId(p[i].index), style);
#if 0
if (ret.empty()) {
WireId wire;
wire.index = decal.index;
log_warning("No gfx decal for wire %s (%d).\n", getWireName(wire).c_str(getCtx()), decal.index);
}
#endif
} }
if (decal.type == DecalId::TYPE_PIP) { if (decal.type == DecalId::TYPE_PIP) {
const PipInfoPOD &p = chip_info->pip_data[decal.index]; const PipInfoPOD &p = chip_info->pip_data[decal.index];
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN; GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
gfxTilePip(ret, p.x, p.y, GfxTileWireId(p.src_seg), GfxTileWireId(p.dst_seg), style); gfxTilePip(ret, p.x, p.y, GfxTileWireId(p.src_seg), GfxTileWireId(p.dst_seg), style);
#if 0
if (ret.empty()) {
PipId pip;
pip.index = decal.index;
log_warning("No gfx decal for pip %s (%d).\n", getPipName(pip).c_str(getCtx()), decal.index);
}
#endif
} }
if (decal.type == DecalId::TYPE_BEL) { if (decal.type == DecalId::TYPE_BEL) {
@ -782,6 +798,36 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
ret.push_back(el); ret.push_back(el);
} }
} }
if (bel_type == id_SB_GB) {
GraphicElement el;
el.type = GraphicElement::TYPE_BOX;
el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
el.x1 = chip_info->bel_data[bel.index].x + local_swbox_x1 + 0.05;
el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2 - 0.05;
el.y1 = chip_info->bel_data[bel.index].y + main_swbox_y2 - 0.05;
el.y2 = chip_info->bel_data[bel.index].y + main_swbox_y2 - 0.10;
ret.push_back(el);
}
if (bel_type == id_ICESTORM_PLL || bel_type == id_SB_WARMBOOT) {
GraphicElement el;
el.type = GraphicElement::TYPE_BOX;
el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
el.x1 = chip_info->bel_data[bel.index].x + local_swbox_x1 + 0.05;
el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2 - 0.05;
el.y1 = chip_info->bel_data[bel.index].y + main_swbox_y2;
el.y2 = chip_info->bel_data[bel.index].y + main_swbox_y2 + 0.05;
ret.push_back(el);
}
#if 0
if (ret.empty()) {
BelId bel;
bel.index = decal.index;
log_warning("No gfx decal for bel %s (%d).\n", getBelName(bel).c_str(getCtx()), decal.index);
}
#endif
} }
return ret; return ret;

4
ice40/chipdb.py
View File

@ -727,10 +727,6 @@ def add_pip(src, dst, flags=0):
pip_xy[(src, dst)] = (x, y, 0, len(switches) - 1, flags) pip_xy[(src, dst)] = (x, y, 0, len(switches) - 1, flags)
# Add virtual padin wires
for i in range(8):
add_wire(0, 0, "padin_%d" % i)
def add_bel_input(bel, wire, port): def add_bel_input(bel, wire, port):
if wire not in wire_belports: if wire not in wire_belports:
wire_belports[wire] = set() wire_belports[wire] = set()

1
ice40/gfx.cc
View File

@ -814,6 +814,7 @@ static bool getWireXY_main(GfxTileWireId id, float &x, float &y)
int idx = id - TILE_WIRE_SPAN4_VERT_B_0; int idx = id - TILE_WIRE_SPAN4_VERT_B_0;
y = 1.0 - (0.03 + 0.0025 * (270 - idx)); y = 1.0 - (0.03 + 0.0025 * (270 - idx));
x = main_swbox_x1; x = main_swbox_x1;
return true;
} }
// Global2Local // Global2Local