Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
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commit
81a154ca5d
@ -53,6 +53,13 @@ inline bool is_sb_io(const CellInfo *cell) { return cell->type == "SB_IO"; }
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// Return true if a cell is a global buffer
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inline bool is_gbuf(const CellInfo *cell) { return cell->type == "SB_GB"; }
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// Return true if a cell is a RAM
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inline bool is_ram(const CellInfo *cell)
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{
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return cell->type == "SB_RAM40_4K" || cell->type == "SB_RAM40_4KNR" ||
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cell->type == "SB_RAM40_4KNW" || cell->type == "SB_RAM40_4KNRNW";
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}
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// Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports
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// as needed. Set no_dff if a DFF is not being used, so that the output
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// can be reconnected
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@ -114,6 +114,23 @@ static void pack_nonlut_ffs(Design *design)
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}
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}
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// "Pack" RAMs
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static void pack_ram(Design *design)
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{
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for (auto cell : design->cells) {
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CellInfo *ci = cell.second;
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if (is_ram(ci)) {
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ci->params["NEG_CLK_W"] =
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std::to_string(ci->type == "SB_RAM40_4KNW" ||
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ci->type == "SB_RAM40_4KNRNW");
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ci->params["NEG_CLK_R"] =
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std::to_string(ci->type == "SB_RAM40_4KNR" ||
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ci->type == "SB_RAM40_4KNRNW");
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ci->type = "ICESTORM_RAM";
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}
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}
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}
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// Merge a net into a constant net
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static void set_net_constant(NetInfo *orig, NetInfo *constnet, bool constval)
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{
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@ -230,6 +247,17 @@ static void pack_io(Design *design)
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}
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}
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static bool is_clock_port(const PortRef &port)
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{
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if (port.cell == nullptr)
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return false;
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if (is_ff(port.cell))
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return port.port == "C";
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if (is_ram(port.cell))
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return port.port == "RCLK" || port.port == "WCLK";
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return false;
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}
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// Simple global promoter (clock only)
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static void promote_globals(Design *design)
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{
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@ -241,8 +269,7 @@ static void promote_globals(Design *design)
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if (ni->driver.cell != nullptr && !is_global_net(ni)) {
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clock_count[net.first] = 0;
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for (auto user : ni->users) {
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if (user.cell != nullptr && is_ff(user.cell) &&
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user.port == "C")
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if (is_clock_port(user))
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clock_count[net.first]++;
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}
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}
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@ -269,7 +296,7 @@ static void promote_globals(Design *design)
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design->nets[glbnet->name] = glbnet;
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std::vector<PortRef> keep_users;
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for (auto user : clknet->users) {
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if (user.cell != nullptr && is_ff(user.cell) && user.port == "C") {
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if (is_clock_port(user)) {
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user.cell->ports[user.port].net = glbnet;
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glbnet->users.push_back(user);
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} else {
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@ -289,6 +316,7 @@ void pack_design(Design *design)
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pack_io(design);
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pack_lut_lutffs(design);
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pack_nonlut_ffs(design);
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pack_ram(design);
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}
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NEXTPNR_NAMESPACE_END
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