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Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr

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This commit is contained in:
Clifford Wolf 2018-06-13 16:54:25 +02:00
commit 81a154ca5d
2 changed files with 38 additions and 3 deletions
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7
ice40/cells.h
View File

@ -53,6 +53,13 @@ inline bool is_sb_io(const CellInfo *cell) { return cell->type == "SB_IO"; }
// Return true if a cell is a global buffer
inline bool is_gbuf(const CellInfo *cell) { return cell->type == "SB_GB"; }
// Return true if a cell is a RAM
inline bool is_ram(const CellInfo *cell)
{
return cell->type == "SB_RAM40_4K" || cell->type == "SB_RAM40_4KNR" ||
cell->type == "SB_RAM40_4KNW" || cell->type == "SB_RAM40_4KNRNW";
}
// Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports
// as needed. Set no_dff if a DFF is not being used, so that the output
// can be reconnected

34
ice40/pack.cc
View File

@ -114,6 +114,23 @@ static void pack_nonlut_ffs(Design *design)
}
}
// "Pack" RAMs
static void pack_ram(Design *design)
{
for (auto cell : design->cells) {
CellInfo *ci = cell.second;
if (is_ram(ci)) {
ci->params["NEG_CLK_W"] =
std::to_string(ci->type == "SB_RAM40_4KNW" ||
ci->type == "SB_RAM40_4KNRNW");
ci->params["NEG_CLK_R"] =
std::to_string(ci->type == "SB_RAM40_4KNR" ||
ci->type == "SB_RAM40_4KNRNW");
ci->type = "ICESTORM_RAM";
}
}
}
// Merge a net into a constant net
static void set_net_constant(NetInfo *orig, NetInfo *constnet, bool constval)
{
@ -230,6 +247,17 @@ static void pack_io(Design *design)
}
}
static bool is_clock_port(const PortRef &port)
{
if (port.cell == nullptr)
return false;
if (is_ff(port.cell))
return port.port == "C";
if (is_ram(port.cell))
return port.port == "RCLK" || port.port == "WCLK";
return false;
}
// Simple global promoter (clock only)
static void promote_globals(Design *design)
{
@ -241,8 +269,7 @@ static void promote_globals(Design *design)
if (ni->driver.cell != nullptr && !is_global_net(ni)) {
clock_count[net.first] = 0;
for (auto user : ni->users) {
if (user.cell != nullptr && is_ff(user.cell) &&
user.port == "C")
if (is_clock_port(user))
clock_count[net.first]++;
}
}
@ -269,7 +296,7 @@ static void promote_globals(Design *design)
design->nets[glbnet->name] = glbnet;
std::vector<PortRef> keep_users;
for (auto user : clknet->users) {
if (user.cell != nullptr && is_ff(user.cell) && user.port == "C") {
if (is_clock_port(user)) {
user.cell->ports[user.port].net = glbnet;
glbnet->users.push_back(user);
} else {
@ -289,6 +316,7 @@ void pack_design(Design *design)
pack_io(design);
pack_lut_lutffs(design);
pack_nonlut_ffs(design);
pack_ram(design);
}
NEXTPNR_NAMESPACE_END