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Merge pull request #947 from antmicro/dcc_enhancements

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nexus: DCC support fixups
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gatecat 2022-03-15 18:54:18 +00:00 committed by GitHub
commit 81b48b414b
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2 changed files with 20 additions and 0 deletions
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8
nexus/arch.cc
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@ -546,6 +546,14 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
if (type == TMG_REGISTER_INPUT || type == TMG_REGISTER_OUTPUT)
clockInfoCount = 1;
return type;
} else if (cell->type == id_DCC) {
if (port == id_CLKI)
return TMG_CLOCK_INPUT;
else if (port == id_CLKO)
return TMG_GEN_CLOCK;
else if (port == id_CE)
return TMG_COMB_INPUT;
return TMG_IGNORE;
}
return TMG_IGNORE;
}

12
nexus/fasm.cc
View File

@ -526,6 +526,16 @@ struct NexusFasmWriter
write_cell_muxes(cell);
pop(2);
}
// Write config for DCC
void write_dcc(const CellInfo *cell)
{
BelId bel = cell->bel;
push_tile(bel.tile);
push_belname(bel);
write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer
write_cell_muxes(cell);
pop(2);
}
// Write config for an OXIDE_EBR cell
void write_bram(const CellInfo *cell)
{
@ -927,6 +937,8 @@ struct NexusFasmWriter
write_dphy(ci);
else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC)
write_iol(ci);
else if (ci->type == id_DCC)
write_dcc(ci);
blank();
}
// Handle DCC route-throughs