Load Torc DDB

This commit is contained in:
Eddie Hung 2018-08-11 15:53:55 -07:00
parent 6425032ec4
commit 8357417787
5 changed files with 66 additions and 12 deletions

View File

@ -28,6 +28,8 @@
#include "router1.h" #include "router1.h"
#include "util.h" #include "util.h"
#include "torc/common/DirectoryTree.hpp"
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
@ -43,8 +45,9 @@ void IdString::initialize_arch(const BaseCtx *ctx)
Arch::Arch(ArchArgs args) : args(args) Arch::Arch(ArchArgs args) : args(args)
{ {
if (args.type == ArchArgs::XC7Z020) { torc::common::DirectoryTree directoryTree("../../torc/src/torc");
//chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)); if (args.type == ArchArgs::Z020) {
ddb = new DDB("xc7z020", "clg484");
} else { } else {
log_error("Unsupported XC7 chip type.\n"); log_error("Unsupported XC7 chip type.\n");
} }
@ -64,8 +67,8 @@ Arch::Arch(ArchArgs args) : args(args)
std::string Arch::getChipName() const std::string Arch::getChipName() const
{ {
if (args.type == ArchArgs::XC7Z020) { if (args.type == ArchArgs::Z020) {
return "XC7Z020"; return "z020";
} else { } else {
log_error("Unsupported XC7 chip type.\n"); log_error("Unsupported XC7 chip type.\n");
} }
@ -75,8 +78,8 @@ std::string Arch::getChipName() const
IdString Arch::archArgsToId(ArchArgs args) const IdString Arch::archArgsToId(ArchArgs args) const
{ {
if (args.type == ArchArgs::XC7Z020) if (args.type == ArchArgs::Z020)
return id("xc7z020"); return id("z020");
return IdString(); return IdString();
} }

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@ -21,6 +21,10 @@
#error Include "arch.h" via "nextpnr.h" only. #error Include "arch.h" via "nextpnr.h" only.
#endif #endif
#include "torc/Architecture.hpp"
#include "torc/Common.hpp"
using namespace torc::architecture;
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
/**** Everything in this section must be kept in sync with chipdb.py ****/ /**** Everything in this section must be kept in sync with chipdb.py ****/
@ -378,7 +382,7 @@ struct ArchArgs
enum ArchArgsTypes enum ArchArgsTypes
{ {
NONE, NONE,
XC7Z020 Z020
} type = NONE; } type = NONE;
std::string package; std::string package;
}; };
@ -387,6 +391,7 @@ struct Arch : BaseCtx
{ {
bool fast_part; bool fast_part;
const ChipInfoPOD *chip_info; const ChipInfoPOD *chip_info;
const DDB *ddb;
const PackageInfoPOD *package_info; const PackageInfoPOD *package_info;
mutable std::unordered_map<IdString, int> bel_by_name; mutable std::unordered_map<IdString, int> bel_by_name;

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@ -0,0 +1,46 @@
include_directories(.)
#include_directories(torc/externals/zlib)
target_link_libraries(
nextpnr-${family}
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Arc.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/ArcUsage.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Array.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/DDB.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/DDBConsoleStreams.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/DDBStreamHelper.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/DigestStream.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/ExtendedWireInfo.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/InstancePin.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/OutputStreamHelpers.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Package.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Pad.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/PrimitiveConn.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/PrimitiveDef.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/PrimitiveElement.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/PrimitiveElementPin.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/PrimitivePin.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Segments.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Site.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Sites.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Tiles.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/TileInfo.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Tilewire.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/Versions.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/VprExporter.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/WireInfo.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/WireUsage.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/XdlImporter.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/architecture/XilinxDatabaseTypes.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/common/Annotated.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/common/DeviceDesignator.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/common/Devices.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/common/DirectoryTree.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/common/DottedVersion.o
PRIVATE ${CMAKE_SOURCE_DIR}/torc/common/NullOutputStream.o
PRIVATE boost_regex
PRIVATE ${CMAKE_SOURCE_DIR}/torc/externals/zlib/zfstream.o
PRIVATE z
)

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@ -82,13 +82,13 @@ void Xc7CommandHandler::setupArchContext(Context *ctx)
std::unique_ptr<Context> Xc7CommandHandler::createContext() std::unique_ptr<Context> Xc7CommandHandler::createContext()
{ {
if (vm.count("xc7z020")) { if (vm.count("z020")) {
chipArgs.type = ArchArgs::XC7Z020; chipArgs.type = ArchArgs::Z020;
chipArgs.package = "clg484"; chipArgs.package = "clg484";
} }
if (chipArgs.type == ArchArgs::NONE) { if (chipArgs.type == ArchArgs::NONE) {
chipArgs.type = ArchArgs::XC7Z020; chipArgs.type = ArchArgs::Z020;
chipArgs.package = "clg484"; chipArgs.package = "clg484";
} }

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@ -38,8 +38,8 @@ std::unique_ptr<Context> ProjectHandler::createContext(pt::ptree &root)
{ {
ArchArgs chipArgs; ArchArgs chipArgs;
std::string arch_type = root.get<std::string>("project.arch.type"); std::string arch_type = root.get<std::string>("project.arch.type");
if (arch_type == "xc7z020") { if (arch_type == "z020") {
chipArgs.type = ArchArgs::XC7Z020; chipArgs.type = ArchArgs::Z020;
} }
chipArgs.package = root.get<std::string>("project.arch.package"); chipArgs.package = root.get<std::string>("project.arch.package");