Remove some more ice40 stuff
This commit is contained in:
Eddie Hung
parent
0514fb9042
commit
84485152cc
34
xc7/arch.cc
34
xc7/arch.cc
@ -442,44 +442,14 @@ BelId Arch::getBelByLocation(Loc loc) const
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
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br.e.cursor = br.b.cursor;
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if (br.e.cursor != -1) {
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while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
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chip_info->bel_data[br.e.cursor].y == y)
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br.e.cursor++;
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}
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NPNR_ASSERT("TODO");
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return br;
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (bel_wires[i].port == pin.index)
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return PortType(bel_wires[i].type);
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}
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} else {
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int b = 0, e = num_bel_wires - 1;
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while (b <= e) {
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int i = (b + e) / 2;
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if (bel_wires[i].port == pin.index)
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return PortType(bel_wires[i].type);
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if (bel_wires[i].port > pin.index)
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e = i - 1;
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else
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b = i + 1;
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}
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}
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NPNR_ASSERT("TODO");
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return PORT_INOUT;
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}
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209
xc7/arch.h
209
xc7/arch.h
@ -64,210 +64,6 @@ template <> struct hash<Arc>
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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int32_t port;
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int32_t type;
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int32_t wire_index;
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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int32_t type;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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int8_t x, y, z;
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int8_t padding_0;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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int32_t bel_index;
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int32_t port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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enum PipFlags : uint32_t
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{
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FLAG_NONE = 0,
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FLAG_ROUTETHRU = 1,
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FLAG_NOCARRY = 2
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};
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// RelPtr<char> name;
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int32_t src, dst;
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int32_t fast_delay;
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int32_t slow_delay;
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int8_t x, y;
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int16_t src_seg, dst_seg;
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int16_t switch_mask;
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int32_t switch_index;
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PipFlags flags;
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});
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NPNR_PACKED_STRUCT(struct WireSegmentPOD {
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int8_t x, y;
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int16_t index;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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enum WireType : int8_t
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{
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WIRE_TYPE_NONE = 0,
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WIRE_TYPE_GLB2LOCAL = 1,
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WIRE_TYPE_GLB_NETWK = 2,
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WIRE_TYPE_LOCAL = 3,
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WIRE_TYPE_LUTFF_IN = 4,
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WIRE_TYPE_LUTFF_IN_LUT = 5,
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WIRE_TYPE_LUTFF_LOUT = 6,
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WIRE_TYPE_LUTFF_OUT = 7,
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WIRE_TYPE_LUTFF_COUT = 8,
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WIRE_TYPE_LUTFF_GLOBAL = 9,
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WIRE_TYPE_CARRY_IN_MUX = 10,
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WIRE_TYPE_SP4_V = 11,
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WIRE_TYPE_SP4_H = 12,
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WIRE_TYPE_SP12_V = 13,
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WIRE_TYPE_SP12_H = 14
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};
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RelPtr<char> name;
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int32_t num_uphill, num_downhill;
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RelPtr<int32_t> pips_uphill, pips_downhill;
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int32_t num_bel_pins;
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RelPtr<BelPortPOD> bel_pins;
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int32_t num_segments;
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RelPtr<WireSegmentPOD> segments;
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int32_t fast_delay;
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int32_t slow_delay;
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int8_t x, y, z;
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WireType type;
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});
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NPNR_PACKED_STRUCT(struct PackagePinPOD {
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RelPtr<char> name;
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int32_t bel_index;
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});
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NPNR_PACKED_STRUCT(struct PackageInfoPOD {
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RelPtr<char> name;
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int32_t num_pins;
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RelPtr<PackagePinPOD> pins;
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});
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enum TileType : uint32_t
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{
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TILE_NONE = 0,
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TILE_LOGIC = 1,
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TILE_IO = 2,
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TILE_RAMB = 3,
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TILE_RAMT = 4,
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TILE_DSP0 = 5,
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TILE_DSP1 = 6,
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TILE_DSP2 = 7,
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TILE_DSP3 = 8,
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TILE_IPCON = 9
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};
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NPNR_PACKED_STRUCT(struct ConfigBitPOD { int8_t row, col; });
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NPNR_PACKED_STRUCT(struct ConfigEntryPOD {
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RelPtr<char> name;
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int32_t num_bits;
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RelPtr<ConfigBitPOD> bits;
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});
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NPNR_PACKED_STRUCT(struct TileInfoPOD {
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int8_t cols, rows;
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int16_t num_config_entries;
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RelPtr<ConfigEntryPOD> entries;
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});
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static const int max_switch_bits = 5;
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NPNR_PACKED_STRUCT(struct SwitchInfoPOD {
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int32_t num_bits;
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int32_t bel;
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int8_t x, y;
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ConfigBitPOD cbits[max_switch_bits];
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});
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NPNR_PACKED_STRUCT(struct IerenInfoPOD {
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int8_t iox, ioy, ioz;
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int8_t ierx, iery, ierz;
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});
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NPNR_PACKED_STRUCT(struct BitstreamInfoPOD {
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int32_t num_switches, num_ierens;
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RelPtr<TileInfoPOD> tiles_nonrouting;
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RelPtr<SwitchInfoPOD> switches;
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RelPtr<IerenInfoPOD> ierens;
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});
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NPNR_PACKED_STRUCT(struct BelConfigEntryPOD {
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RelPtr<char> entry_name;
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RelPtr<char> cbit_name;
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int8_t x, y;
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int16_t padding;
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});
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// Stores mapping between bel parameters and config bits,
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// for extra cells where this mapping is non-trivial
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NPNR_PACKED_STRUCT(struct BelConfigPOD {
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int32_t bel_index;
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int32_t num_entries;
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RelPtr<BelConfigEntryPOD> entries;
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});
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NPNR_PACKED_STRUCT(struct CellPathDelayPOD {
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int32_t from_port;
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int32_t to_port;
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int32_t fast_delay;
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int32_t slow_delay;
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});
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NPNR_PACKED_STRUCT(struct CellTimingPOD {
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int32_t type;
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int32_t num_paths;
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RelPtr<CellPathDelayPOD> path_delays;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_bels, num_wires, num_pips;
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int32_t num_switches, num_belcfgs, num_packages;
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int32_t num_timing_cells;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pip_data;
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RelPtr<TileType> tile_grid;
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RelPtr<BitstreamInfoPOD> bits_info;
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RelPtr<BelConfigPOD> bel_config;
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RelPtr<PackageInfoPOD> packages_data;
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RelPtr<CellTimingPOD> cell_timing;
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});
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struct TorcInfo
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{
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TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName);
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@ -339,8 +135,6 @@ struct TorcInfo
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};
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extern std::unique_ptr<const TorcInfo> torc_info;
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/************************ End of chipdb section. ************************/
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struct BelIterator
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{
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int cursor;
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@ -485,9 +279,6 @@ struct ArchArgs
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struct Arch : BaseCtx
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{
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bool fast_part;
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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int width;
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int height;
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@ -77,7 +77,7 @@ class ChainConstrainer
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bool start_of_chain = true;
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std::vector<CellChain> chains;
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std::vector<const CellInfo *> tile;
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const int max_length = (ctx->chip_info->height - 2) * 8 - 2;
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const int max_length = (torc_info->height - 2) * 8 - 2;
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auto curr_cell = carryc.cells.begin();
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while (curr_cell != carryc.cells.end()) {
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CellInfo *cell = *curr_cell;
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1280
xc7/chipdb.py
1280
xc7/chipdb.py
File diff suppressed because it is too large
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