Remove some more ice40 stuff

xc7/arch.cc

@@ -442,44 +442,14 @@ BelId Arch::getBelByLocation(Loc loc) const
 BelRange Arch::getBelsByTile(int x, int y) const
 {
     BelRange br;
-
+    NPNR_ASSERT("TODO");
-    br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
-    br.e.cursor = br.b.cursor;
-
-    if (br.e.cursor != -1) {
-        while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
-               chip_info->bel_data[br.e.cursor].y == y)
-            br.e.cursor++;
-    }
-
     return br;
 }
 
 PortType Arch::getBelPinType(BelId bel, IdString pin) const
 {
     NPNR_ASSERT(bel != BelId());
-
+    NPNR_ASSERT("TODO");
-    int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
-    const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
-
-    if (num_bel_wires < 7) {
-        for (int i = 0; i < num_bel_wires; i++) {
-            if (bel_wires[i].port == pin.index)
-                return PortType(bel_wires[i].type);
-        }
-    } else {
-        int b = 0, e = num_bel_wires - 1;
-        while (b <= e) {
-            int i = (b + e) / 2;
-            if (bel_wires[i].port == pin.index)
-                return PortType(bel_wires[i].type);
-            if (bel_wires[i].port > pin.index)
-                e = i - 1;
-            else
-                b = i + 1;
-        }
-    }
-
     return PORT_INOUT;
 }
 

xc7/arch.h

@@ -64,210 +64,6 @@ template <> struct hash<Arc>
 
 NEXTPNR_NAMESPACE_BEGIN
 
-/**** Everything in this section must be kept in sync with chipdb.py ****/
-
-template <typename T> struct RelPtr
-{
-    int32_t offset;
-
-    // void set(const T *ptr) {
-    //     offset = reinterpret_cast<const char*>(ptr) -
-    //              reinterpret_cast<const char*>(this);
-    // }
-
-    const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
-
-    const T &operator[](size_t index) const { return get()[index]; }
-
-    const T &operator*() const { return *(get()); }
-
-    const T *operator->() const { return get(); }
-};
-
-NPNR_PACKED_STRUCT(struct BelWirePOD {
-    int32_t port;
-    int32_t type;
-    int32_t wire_index;
-});
-
-NPNR_PACKED_STRUCT(struct BelInfoPOD {
-    RelPtr<char> name;
-    int32_t type;
-    int32_t num_bel_wires;
-    RelPtr<BelWirePOD> bel_wires;
-    int8_t x, y, z;
-    int8_t padding_0;
-});
-
-NPNR_PACKED_STRUCT(struct BelPortPOD {
-    int32_t bel_index;
-    int32_t port;
-});
-
-NPNR_PACKED_STRUCT(struct PipInfoPOD {
-    enum PipFlags : uint32_t
-    {
-        FLAG_NONE = 0,
-        FLAG_ROUTETHRU = 1,
-        FLAG_NOCARRY = 2
-    };
-
-    // RelPtr<char> name;
-    int32_t src, dst;
-    int32_t fast_delay;
-    int32_t slow_delay;
-    int8_t x, y;
-    int16_t src_seg, dst_seg;
-    int16_t switch_mask;
-    int32_t switch_index;
-    PipFlags flags;
-});
-
-NPNR_PACKED_STRUCT(struct WireSegmentPOD {
-    int8_t x, y;
-    int16_t index;
-});
-
-NPNR_PACKED_STRUCT(struct WireInfoPOD {
-    enum WireType : int8_t
-    {
-        WIRE_TYPE_NONE = 0,
-        WIRE_TYPE_GLB2LOCAL = 1,
-        WIRE_TYPE_GLB_NETWK = 2,
-        WIRE_TYPE_LOCAL = 3,
-        WIRE_TYPE_LUTFF_IN = 4,
-        WIRE_TYPE_LUTFF_IN_LUT = 5,
-        WIRE_TYPE_LUTFF_LOUT = 6,
-        WIRE_TYPE_LUTFF_OUT = 7,
-        WIRE_TYPE_LUTFF_COUT = 8,
-        WIRE_TYPE_LUTFF_GLOBAL = 9,
-        WIRE_TYPE_CARRY_IN_MUX = 10,
-        WIRE_TYPE_SP4_V = 11,
-        WIRE_TYPE_SP4_H = 12,
-        WIRE_TYPE_SP12_V = 13,
-        WIRE_TYPE_SP12_H = 14
-    };
-
-    RelPtr<char> name;
-    int32_t num_uphill, num_downhill;
-    RelPtr<int32_t> pips_uphill, pips_downhill;
-
-    int32_t num_bel_pins;
-    RelPtr<BelPortPOD> bel_pins;
-
-    int32_t num_segments;
-    RelPtr<WireSegmentPOD> segments;
-
-    int32_t fast_delay;
-    int32_t slow_delay;
-
-    int8_t x, y, z;
-    WireType type;
-});
-
-NPNR_PACKED_STRUCT(struct PackagePinPOD {
-    RelPtr<char> name;
-    int32_t bel_index;
-});
-
-NPNR_PACKED_STRUCT(struct PackageInfoPOD {
-    RelPtr<char> name;
-    int32_t num_pins;
-    RelPtr<PackagePinPOD> pins;
-});
-
-enum TileType : uint32_t
-{
-    TILE_NONE = 0,
-    TILE_LOGIC = 1,
-    TILE_IO = 2,
-    TILE_RAMB = 3,
-    TILE_RAMT = 4,
-    TILE_DSP0 = 5,
-    TILE_DSP1 = 6,
-    TILE_DSP2 = 7,
-    TILE_DSP3 = 8,
-    TILE_IPCON = 9
-};
-
-NPNR_PACKED_STRUCT(struct ConfigBitPOD { int8_t row, col; });
-
-NPNR_PACKED_STRUCT(struct ConfigEntryPOD {
-    RelPtr<char> name;
-    int32_t num_bits;
-    RelPtr<ConfigBitPOD> bits;
-});
-
-NPNR_PACKED_STRUCT(struct TileInfoPOD {
-    int8_t cols, rows;
-    int16_t num_config_entries;
-    RelPtr<ConfigEntryPOD> entries;
-});
-
-static const int max_switch_bits = 5;
-
-NPNR_PACKED_STRUCT(struct SwitchInfoPOD {
-    int32_t num_bits;
-    int32_t bel;
-    int8_t x, y;
-    ConfigBitPOD cbits[max_switch_bits];
-});
-
-NPNR_PACKED_STRUCT(struct IerenInfoPOD {
-    int8_t iox, ioy, ioz;
-    int8_t ierx, iery, ierz;
-});
-
-NPNR_PACKED_STRUCT(struct BitstreamInfoPOD {
-    int32_t num_switches, num_ierens;
-    RelPtr<TileInfoPOD> tiles_nonrouting;
-    RelPtr<SwitchInfoPOD> switches;
-    RelPtr<IerenInfoPOD> ierens;
-});
-
-NPNR_PACKED_STRUCT(struct BelConfigEntryPOD {
-    RelPtr<char> entry_name;
-    RelPtr<char> cbit_name;
-    int8_t x, y;
-    int16_t padding;
-});
-
-// Stores mapping between bel parameters and config bits,
-// for extra cells where this mapping is non-trivial
-NPNR_PACKED_STRUCT(struct BelConfigPOD {
-    int32_t bel_index;
-    int32_t num_entries;
-    RelPtr<BelConfigEntryPOD> entries;
-});
-
-NPNR_PACKED_STRUCT(struct CellPathDelayPOD {
-    int32_t from_port;
-    int32_t to_port;
-    int32_t fast_delay;
-    int32_t slow_delay;
-});
-
-NPNR_PACKED_STRUCT(struct CellTimingPOD {
-    int32_t type;
-    int32_t num_paths;
-    RelPtr<CellPathDelayPOD> path_delays;
-});
-
-NPNR_PACKED_STRUCT(struct ChipInfoPOD {
-    int32_t width, height;
-    int32_t num_bels, num_wires, num_pips;
-    int32_t num_switches, num_belcfgs, num_packages;
-    int32_t num_timing_cells;
-    RelPtr<BelInfoPOD> bel_data;
-    RelPtr<WireInfoPOD> wire_data;
-    RelPtr<PipInfoPOD> pip_data;
-    RelPtr<TileType> tile_grid;
-    RelPtr<BitstreamInfoPOD> bits_info;
-    RelPtr<BelConfigPOD> bel_config;
-    RelPtr<PackageInfoPOD> packages_data;
-    RelPtr<CellTimingPOD> cell_timing;
-});
-
 struct TorcInfo
 {
     TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName);
@@ -339,8 +135,6 @@ struct TorcInfo
 };
 extern std::unique_ptr<const TorcInfo> torc_info;
 
-/************************ End of chipdb section. ************************/
-
 struct BelIterator
 {
     int cursor;
@@ -485,9 +279,6 @@ struct ArchArgs
 
 struct Arch : BaseCtx
 {
-    bool fast_part;
-    const ChipInfoPOD *chip_info;
-    const PackageInfoPOD *package_info;
     int width;
     int height;
 

xc7/chains.cc

@@ -77,7 +77,7 @@ class ChainConstrainer
         bool start_of_chain = true;
         std::vector<CellChain> chains;
         std::vector<const CellInfo *> tile;
-        const int max_length = (ctx->chip_info->height - 2) * 8 - 2;
+        const int max_length = (torc_info->height - 2) * 8 - 2;
         auto curr_cell = carryc.cells.begin();
         while (curr_cell != carryc.cells.end()) {
             CellInfo *cell = *curr_cell;