Add implicit wire

2018-12-27 23:27:50 -08:00 · 2018-12-27 23:27:50 -08:00 · 84d038360d
commit 84d038360d
parent e15aa8d3f4
1 changed files with 1 additions and 0 deletions
--- a/xc7/blinky.v
+++ b/xc7/blinky.v
@ -5,6 +5,7 @@ module blinky (
    output led2,
    output led3
 );
+    wire clk;
    BUFGCTRL clk_gb (
        .I0(clki),
        .CE0(1'b1),