Minor refactoring of BinaryBlobAssembler, fix alignments
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
69e5bc5030
commit
84defd3fee
@ -31,7 +31,7 @@ const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
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const std::string &name)
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{
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for (int i = 0; i < tile.num_config_entries; i++) {
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if (std::string(tile.entries[i].name.ptr()) == name) {
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if (std::string(tile.entries[i].name.get()) == name) {
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return tile.entries[i];
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}
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}
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@ -153,7 +153,7 @@ BelId Chip::getBelByName(IdString name) const
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if (bel_by_name.empty()) {
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for (int i = 0; i < chip_info.num_bels; i++)
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bel_by_name[chip_info.bel_data[i].name.ptr()] = i;
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bel_by_name[chip_info.bel_data[i].name.get()] = i;
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}
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auto it = bel_by_name.find(name);
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@ -190,7 +190,7 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
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assert(bel != BelId());
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int num_bel_wires = chip_info.bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.ptr();
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const BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++)
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if (bel_wires[i].port == pin) {
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@ -264,7 +264,7 @@ IdString Chip::getPipName(PipId pip) const
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BelId Chip::getPackagePinBel(const std::string &pin) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pins[i].name.ptr() == pin) {
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if (package_info->pins[i].name.get() == pin) {
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BelId id;
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id.index = package_info->pins[i].bel_index;
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return id;
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@ -277,7 +277,7 @@ std::string Chip::getBelPackagePin(BelId bel) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pins[i].bel_index == bel.index) {
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return std::string(package_info->pins[i].name.ptr());
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return std::string(package_info->pins[i].name.get());
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}
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}
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return "";
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29
ice40/chip.h
29
ice40/chip.h
@ -72,27 +72,30 @@ PortPin portPinFromId(IdString id);
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// -----------------------------------------------------------------------
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T>
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struct RelPtr {
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int offset;
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int32_t offset;
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// RelPtr(const T *ptr) : offset(reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this)) {}
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) - reinterpret_cast<const char*>(this);
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// }
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const T*get() const {
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return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
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}
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const T&operator[](size_t index) const {
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return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset)[index];
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return get()[index];
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}
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const T&operator*() const {
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return *reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
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return *(get());
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}
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const T*operator->() const {
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return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
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}
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const T*ptr() const {
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return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
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return get();
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}
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};
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@ -109,7 +112,7 @@ struct BelInfoPOD
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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int8_t x, y, z;
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int8_t filler_0;
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int8_t padding_0;
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} __attribute__((packed));
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struct BelPortPOD
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@ -222,6 +225,8 @@ extern ChipInfoPOD chip_info_1k;
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extern ChipInfoPOD chip_info_5k;
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extern ChipInfoPOD chip_info_8k;
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/************************ End of chipdb section. ************************/
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// -----------------------------------------------------------------------
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struct BelId
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@ -481,7 +486,7 @@ struct Chip
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IdString getBelName(BelId bel) const
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{
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assert(bel != BelId());
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return chip_info.bel_data[bel.index].name.ptr();
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return chip_info.bel_data[bel.index].name.get();
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}
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void bindBel(BelId bel, IdString cell)
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188
ice40/chipdb.py
188
ice40/chipdb.py
@ -5,6 +5,7 @@ import re
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import textwrap
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endianness = "le"
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compact_output = True
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dev_name = None
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dev_width = None
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@ -366,23 +367,36 @@ elif dev_name == "384":
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add_bel_gb( 3, 9, 4)
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class BinaryBlobAssembler:
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def __init__(self):
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def __init__(self, cname, endianness, ctype = "unsigned char"):
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assert endianness in ["le", "be"]
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self.cname = cname
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self.ctype = ctype
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self.endianness = endianness
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self.finalized = False
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self.data = bytearray()
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self.comments = dict()
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self.labels = dict()
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self.exports = set()
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self.labels_byaddr = dict()
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self.ltypes_byaddr = dict()
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self.strings = dict()
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self.refs = dict()
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def l(self, name, ltype = None):
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def l(self, name, ltype = None, export = False):
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assert not self.finalized
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assert name not in self.labels
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assert len(self.data) not in self.labels_byaddr
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self.labels[name] = len(self.data)
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if ltype is not None:
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self.ltypes_byaddr[len(self.data)] = ltype
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self.labels_byaddr[len(self.data)] = name
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if export:
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assert ltype is not None
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self.exports.add(len(self.data))
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def r(self, name, comment):
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assert not self.finalized
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assert len(self.data) % 4 == 0
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assert len(self.data) not in self.refs
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self.refs[len(self.data)] = (name, comment)
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self.data.append(0)
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@ -390,23 +404,28 @@ class BinaryBlobAssembler:
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self.data.append(0)
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self.data.append(0)
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def s(self, v, comment):
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for i in range(len(v)):
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self.data.append(ord(v[i]))
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self.data.append(0)
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if comment is not None:
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self.comments[len(self.data)] = comment
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def s(self, s, comment):
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assert not self.finalized
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if s not in self.strings:
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index = len(self.strings)
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self.strings[s] = index
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else:
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index = self.strings[s]
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self.r("str%d" % index, '%s: "%s"' % (comment, s))
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def u8(self, v, comment):
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assert not self.finalized
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self.data.append(v)
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if comment is not None:
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self.comments[len(self.data)] = comment
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def u16(self, v, comment):
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if endianness == "le":
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assert not self.finalized
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assert len(self.data) % 2 == 0
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if self.endianness == "le":
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self.data.append(v & 255)
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self.data.append((v >> 8) & 255)
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elif endianness == "be":
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elif self.endianness == "be":
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self.data.append((v >> 8) & 255)
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self.data.append(v & 255)
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else:
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@ -415,12 +434,14 @@ class BinaryBlobAssembler:
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self.comments[len(self.data)] = comment
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def u32(self, v, comment):
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if endianness == "le":
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assert not self.finalized
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assert len(self.data) % 4 == 0
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if self.endianness == "le":
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self.data.append(v & 255)
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self.data.append((v >> 8) & 255)
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self.data.append((v >> 16) & 255)
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self.data.append((v >> 24) & 255)
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elif endianness == "be":
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elif self.endianness == "be":
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self.data.append((v >> 24) & 255)
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self.data.append((v >> 16) & 255)
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self.data.append((v >> 8) & 255)
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@ -430,53 +451,95 @@ class BinaryBlobAssembler:
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if comment is not None:
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self.comments[len(self.data)] = comment
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def write_c(self, f):
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def finalize(self):
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assert not self.finalized
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for s, index in self.strings.items():
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self.l("str%d" % index, "char")
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for c in s:
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self.data.append(ord(c))
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self.data.append(0)
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self.finalized = True
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cursor = 0
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while cursor < len(self.data):
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if cursor in self.refs:
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v = self.labels[self.refs[cursor][0]] - cursor
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if self.endianness == "le":
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self.data[cursor+0] = (v & 255)
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self.data[cursor+1] = ((v >> 8) & 255)
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self.data[cursor+2] = ((v >> 16) & 255)
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self.data[cursor+3] = ((v >> 24) & 255)
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elif self.endianness == "be":
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self.data[cursor+0] = ((v >> 24) & 255)
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self.data[cursor+1] = ((v >> 16) & 255)
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self.data[cursor+2] = ((v >> 8) & 255)
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self.data[cursor+3] = (v & 255)
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else:
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assert 0
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cursor += 4
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else:
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cursor += 1
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def write_verbose_c(self, f):
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assert self.finalized
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print("%s %s[%d] = {" % (self.ctype, self.cname, len(self.data)), file=f)
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cursor = 0
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bytecnt = 0
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while cursor < len(self.data):
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if cursor in self.comments:
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if bytecnt == 0:
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print(" ", end="")
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print(" // %s" % self.comments[cursor])
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print(" ", end="", file=f)
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print(" // %s" % self.comments[cursor], file=f)
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bytecnt = 0
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if cursor in self.labels_byaddr:
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if bytecnt != 0:
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print()
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if cursor in self.ltypes_byaddr:
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print("#define %s ((%s*)(binblob_%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], dev_name, cursor))
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print(file=f)
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if cursor in self.exports:
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print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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else:
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print(" // [%d] %s" % (cursor, self.labels_byaddr[cursor]))
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print(" // [%d] %s" % (cursor, self.labels_byaddr[cursor]), file=f)
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bytecnt = 0
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if cursor in self.refs:
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v = self.labels[self.refs[cursor][0]] - cursor
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if bytecnt != 0:
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print()
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print(" ", end="")
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if endianness == "le":
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print(" %3d," % (v & 255), end="")
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print(" %3d," % ((v >> 8) & 255), end="")
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print(" %3d," % ((v >> 16) & 255), end="")
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print(" %3d," % ((v >> 24) & 255), end="")
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elif endianness == "be":
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print(" %3d," % (v & 255), end="")
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print(" %3d," % ((v >> 8) & 255), end="")
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print(" %3d," % ((v >> 16) & 255), end="")
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print(" %3d," % ((v >> 24) & 255), end="")
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else:
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assert 0
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print(" // [%d] %s (reference to %s)" % (cursor, self.refs[cursor][1], self.refs[cursor][0]))
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print(file=f)
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print(" ", end="", file=f)
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print(" %-4s" % ("%d," % self.data[cursor+0]), end="", file=f)
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print(" %-4s" % ("%d," % self.data[cursor+1]), end="", file=f)
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print(" %-4s" % ("%d," % self.data[cursor+2]), end="", file=f)
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print(" %-4s" % ("%d," % self.data[cursor+3]), end="", file=f)
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print(" // [%d] %s (reference to %s)" % (cursor, self.refs[cursor][1], self.refs[cursor][0]), file=f)
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bytecnt = 0
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cursor += 4
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else:
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if bytecnt == 0:
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print(" ", end="")
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print(" %3d," % self.data[cursor], end=("" if bytecnt < 15 else "\n"))
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print(" ", end="", file=f)
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print(" %-4s" % ("%d," % self.data[cursor]), end=("" if bytecnt < 15 else "\n"), file=f)
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bytecnt = (bytecnt + 1) & 15
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cursor += 1
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if bytecnt != 0:
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print()
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print(file=f)
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print("};", file=f)
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bba = BinaryBlobAssembler()
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def write_compact_c(self, f):
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assert self.finalized
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print("%s %s[%d] = {" % (self.ctype, self.cname, len(self.data)), file=f)
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column = 0
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for v in self.data:
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if column == 0:
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print(" ", end="", file=f)
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column += 2
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s = "%d," % v
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print(s, end="", file=f)
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column += len(s)
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if column > 75:
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print(file=f)
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column = 0
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if column != 0:
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print(file=f)
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for cursor in self.exports:
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print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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print("};", file=f)
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bba = BinaryBlobAssembler("binblob_%s" % dev_name, endianness, "static uint8_t")
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print('#include "nextpnr.h"')
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print('namespace {')
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@ -490,20 +553,16 @@ for bel in range(len(bel_name)):
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bba.u32(portpins[bel_wires[bel][i][1]], "port")
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index += 1
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bba.l("bel_data", "BelInfoPOD", export=True)
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for bel in range(len(bel_name)):
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bba.l("bel_name_%d" % bel, "char")
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bba.s(bel_name[bel], "name: %s" % bel_name[bel])
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bba.l("bel_data", "BelInfoPOD")
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for bel in range(len(bel_name)):
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bba.r("bel_name_%d" % bel, "name")
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bba.s(bel_name[bel], "name")
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bba.u32(beltypes[bel_type[bel]], "type")
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bba.u32(len(bel_wires[bel]), "num_bel_wires")
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bba.r("bel_wires_%d" % bel, "bel_wires")
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bba.u8(bel_pos[bel][0], "x")
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bba.u8(bel_pos[bel][1], "y")
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bba.u8(bel_pos[bel][2], "z")
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bba.u8(0, "filler")
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bba.u8(0, "padding")
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wireinfo = list()
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pipinfo = list()
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@ -519,7 +578,7 @@ for wire in range(num_wires):
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pips.append(pipcache[(src, wire)])
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num_uphill = len(pips)
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list_uphill = "wire%d_uppips" % wire
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bba.l(list_uphill, "int32_t")
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bba.l(list_uphill, "int32_t", export=True)
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for p in pips:
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bba.u32(p, None)
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else:
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@ -535,7 +594,7 @@ for wire in range(num_wires):
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pips.append(pipcache[(wire, dst)])
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num_downhill = len(pips)
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list_downhill = "wire%d_downpips" % wire
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bba.l(list_downhill, "int32_t")
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bba.l(list_downhill, "int32_t", export=True)
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for p in pips:
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bba.u32(p, None)
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else:
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@ -544,7 +603,7 @@ for wire in range(num_wires):
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if wire in wire_downhill_belports:
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num_bels_downhill = len(wire_downhill_belports[wire])
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bba.l("wire%d_downbels" % wire, "BelPortPOD")
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bba.l("wire%d_downbels" % wire, "BelPortPOD", export=True)
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for belport in wire_downhill_belports[wire]:
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bba.u32(belport[0], "bel_index")
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bba.u32(portpins[belport[1]], "port")
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@ -585,12 +644,9 @@ for package in packages:
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pin_bel = "X%d/Y%d/io%d" % (x, y, z)
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bel_idx = bel_name.index(pin_bel)
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pins_info.append((pinname, bel_idx))
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bba.l("package_%s_pins" % safename, "PackagePinPOD", export=True)
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for pi in pins_info:
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bba.l("package_%s_pins_%s" % (safename, pi[0]), "char")
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bba.s(pi[0], None)
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bba.l("package_%s_pins" % safename, "PackagePinPOD")
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for pi in pins_info:
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bba.r("package_%s_pins_%s" % (safename, pi[0]), "name")
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bba.s(pi[0], "name")
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bba.u32(pi[1], "bel_index")
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packageinfo.append('{"%s", %d, package_%s_pins}' % (name, len(pins_info), safename))
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@ -613,24 +669,24 @@ for t in range(num_tile_types):
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bba.u8(row, "row")
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bba.u8(col, "col")
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if len(bits) == 0:
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bba.u8(0, "dummy")
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bba.u32(0, "padding")
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elif len(bits) % 2 == 1:
|
||||
bba.u16(0, "padding")
|
||||
centries_info.append((name, len(bits), t, safename))
|
||||
for name, _, t, safename in centries_info:
|
||||
if ("str_%s" % safename) not in bba.labels:
|
||||
bba.l("str_%s" % safename, "char")
|
||||
bba.s(name, None)
|
||||
bba.l("tile%d_config" % t, "ConfigEntryPOD")
|
||||
for _, num_bits, t, safename in centries_info:
|
||||
bba.r("str_%s" % safename, "name")
|
||||
bba.l("tile%d_config" % t, "ConfigEntryPOD", export=True)
|
||||
for name, num_bits, t, safename in centries_info:
|
||||
bba.s(name, "name")
|
||||
bba.u32(num_bits, "num_bits")
|
||||
bba.r("tile%d_%s_bits" % (t, safename), "num_bits")
|
||||
if len(centries_info) == 0:
|
||||
bba.u8(0, "dummy")
|
||||
bba.u32(0, "padding")
|
||||
tileinfo.append("{%d, %d, %d, tile%d_config}" % (tile_sizes[t][0], tile_sizes[t][1], len(centries_info), t))
|
||||
|
||||
print("static uint8_t binblob_%s[] = {" % dev_name)
|
||||
bba.write_c(sys.stdout)
|
||||
print("};")
|
||||
bba.finalize()
|
||||
if compact_output:
|
||||
bba.write_compact_c(sys.stdout)
|
||||
else:
|
||||
bba.write_verbose_c(sys.stdout)
|
||||
|
||||
switchinfo = []
|
||||
switchid = 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user