caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

interchange: Debug IO port validity check failures

Browse Source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-07-12 11:40:23 +01:00
parent 96a5885051
commit 8604b03008
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
fpga_interchange/arch_pack_io.cc
View File

@ -246,7 +246,8 @@ void Arch::pack_ports()
if (possible_site_types.empty()) { if (possible_site_types.empty()) {
if (getCtx()->verbose) if (getCtx()->verbose)
log_info("Port '%s' has no possible site types, falling back to all types!\n", port_name.c_str(getCtx())); log_info("Port '%s' has no possible site types, falling back to all types!\n",
port_name.c_str(getCtx()));
possible_site_types = package_pin_site_types; possible_site_types = package_pin_site_types;
} }
@ -316,6 +317,7 @@ void Arch::pack_ports()
for (CellInfo *cell : placed_cells) { for (CellInfo *cell : placed_cells) {
NPNR_ASSERT(cell->bel != BelId()); NPNR_ASSERT(cell->bel != BelId());
if (!isBelLocationValid(cell->bel)) { if (!isBelLocationValid(cell->bel)) {
explain_bel_status(cell->bel);
log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel)); log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel));
} }
} }

4
fpga_interchange/dedicated_interconnect.cc
View File

@ -457,12 +457,12 @@ void DedicatedInterconnect::explain_bel_status(BelId bel, const CellInfo *cell)
// Only check sink BELs. // Only check sink BELs.
if (net->driver.cell == cell && net->driver.port == port_name) { if (net->driver.cell == cell && net->driver.port == port_name) {
if (!is_driver_on_net_valid(bel, cell, port_name, net)) { if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
log_info("Driver %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx), log_info("Driver %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
net->name.c_str(ctx)); net->name.c_str(ctx));
} }
} else { } else {
if (!is_sink_on_net_valid(bel, cell, port_name, net)) { if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
log_info("Sink %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx), log_info("Sink %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
net->name.c_str(ctx)); net->name.c_str(ctx));
} }
} }