cyclonev: Outline LAB structure
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
parent
c671961c18
commit
86ce6abf6a
@ -261,7 +261,7 @@ bool Arch::pack() { return true; }
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bool Arch::place() { return true; }
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bool Arch::place() { return true; }
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bool Arch::route() { return true; }
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bool Arch::route() { return true; }
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BelId Arch::add_bel(int x, int y, IdString name, IdString type, IdString bucket)
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BelId Arch::add_bel(int x, int y, IdString name, IdString type)
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{
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{
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// TODO: nothing else is using this BelId system yet...
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// TODO: nothing else is using this BelId system yet...
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// TODO (tomorrow?): we probably want a belsByTile type arrangement, similar for wires and pips, for better spacial
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// TODO (tomorrow?): we probably want a belsByTile type arrangement, similar for wires and pips, for better spacial
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@ -274,7 +274,7 @@ BelId Arch::add_bel(int x, int y, IdString name, IdString type, IdString bucket)
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auto &bel = bels[id];
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auto &bel = bels[id];
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bel.name = name;
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bel.name = name;
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bel.type = type;
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bel.type = type;
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bel.bucket = bucket;
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bel.bucket = type;
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return id;
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return id;
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}
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}
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@ -49,6 +49,10 @@ struct ALMInfo
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struct LABInfo
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struct LABInfo
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{
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{
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std::array<ALMInfo, 10> alms;
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std::array<ALMInfo, 10> alms;
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// Control set wires
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std::array<WireId, 3> clk_wires, ena_wires;
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std::array<WireId, 2> aclr_wires;
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WireId sclr_wire, sload_wire;
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// TODO: LAB configuration (control set etc)
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// TODO: LAB configuration (control set etc)
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};
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};
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@ -74,7 +78,7 @@ struct BelInfo
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uint32_t lab; // index into the list of LABs
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uint32_t lab; // index into the list of LABs
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uint8_t alm; // ALM index inside LAB
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uint8_t alm; // ALM index inside LAB
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uint8_t idx; // LUT or FF index inside ALM
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uint8_t idx; // LUT or FF index inside ALM
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} labData;
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} lab_data;
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};
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};
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};
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};
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@ -304,12 +308,17 @@ struct Arch : BaseArch<ArchRanges>
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// -------------------------------------------------
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// -------------------------------------------------
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// Functions for device setup
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// Functions for device setup
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BelId add_bel(int x, int y, IdString name, IdString type, IdString bucket);
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BelId add_bel(int x, int y, IdString name, IdString type);
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WireId add_wire(int x, int y, IdString name, uint64_t flags = 0);
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WireId add_wire(int x, int y, IdString name, uint64_t flags = 0);
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PipId add_pip(WireId src, WireId dst);
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PipId add_pip(WireId src, WireId dst);
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void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
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void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
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WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
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{
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return WireId(cyclonev->pnode_to_rnode(CycloneV::pnode(bt, x, y, port, bi, pi)));
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}
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void create_lab(int x, int y);
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void create_lab(int x, int y);
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void create_gpio(int x, int y);
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void create_gpio(int x, int y);
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@ -323,6 +332,9 @@ struct Arch : BaseArch<ArchRanges>
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std::unordered_map<WireId, WireInfo> wires;
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std::unordered_map<WireId, WireInfo> wires;
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std::unordered_map<BelId, BelInfo> bels;
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std::unordered_map<BelId, BelInfo> bels;
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// List of LABs
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std::vector<LABInfo> labs;
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// WIP to link without failure
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// WIP to link without failure
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std::vector<BelPin> empty_belpin_list;
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std::vector<BelPin> empty_belpin_list;
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@ -36,6 +36,11 @@ X(SHAREIN)
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X(COUT)
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X(COUT)
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X(SHAREOUT)
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X(SHAREOUT)
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X(CARRY_START)
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X(SHARE_START)
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X(CARRY_END)
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X(SHARE_END)
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X(MISTRAL_ALUT6)
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X(MISTRAL_ALUT6)
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X(MISTRAL_ALUT5)
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X(MISTRAL_ALUT5)
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X(MISTRAL_ALUT4)
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X(MISTRAL_ALUT4)
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186
cyclonev/lab.cc
Normal file
186
cyclonev/lab.cc
Normal file
@ -0,0 +1,186 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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// This file contains functions related to our custom LAB structure, including creating the LAB bels; checking the
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// legality of LABs; and manipulating LUT inputs and equations
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namespace {
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static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
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{
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auto &lab = arch->labs.at(lab_idx);
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// Create the combinational part of ALMs.
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// There are two of these, for the two LUT outputs, and these also contain the carry chain and associated logic
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// Each one has all 8 ALM inputs as input pins. In many cases only a subset of these are used; depending on mode;
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// and the bel-cell pin mappings are used to handle this post-placement without losing flexibility
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for (int i = 0; i < 2; i++) {
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// Carry/share wires are a bit tricky due to all the different permutations
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WireId carry_in, share_in;
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WireId carry_out, share_out;
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if (z == 0 && i == 0) {
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if (y == 0) {
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// Base case
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carry_in = arch->add_wire(x, y, id_CARRY_START);
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share_in = arch->add_wire(x, y, id_CARRY_START);
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} else {
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// Output of last tile
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carry_in = arch->add_wire(x, y - 1, id_COUT);
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share_in = arch->add_wire(x, y - 1, id_SHAREOUT);
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}
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} else {
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// Output from last combinational unit
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carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1)));
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share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1)));
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}
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if (z == 9 && i == 1) {
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carry_out = arch->add_wire(x, y, id_COUT);
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share_out = arch->add_wire(x, y, id_SHAREOUT);
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} else {
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carry_out = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", z * 2 + i)));
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share_out = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", z * 2 + i)));
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}
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BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_COMB%d", z, i)), id_MISTRAL_COMB);
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// LUT/MUX inputs
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arch->add_bel_pin(bel, id_A, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::A));
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arch->add_bel_pin(bel, id_B, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::B));
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arch->add_bel_pin(bel, id_C, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::C));
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arch->add_bel_pin(bel, id_D, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::D));
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arch->add_bel_pin(bel, id_E0, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::E0));
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arch->add_bel_pin(bel, id_E1, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::E1));
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arch->add_bel_pin(bel, id_F0, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::F0));
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arch->add_bel_pin(bel, id_F1, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::F1));
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// Carry/share chain
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arch->add_bel_pin(bel, id_CIN, PORT_IN, carry_in);
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arch->add_bel_pin(bel, id_SHAREIN, PORT_IN, share_in);
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arch->add_bel_pin(bel, id_CIN, PORT_OUT, carry_in);
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arch->add_bel_pin(bel, id_SHAREIN, PORT_OUT, share_out);
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// Combinational output
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WireId comb_out = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i)));
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arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, comb_out);
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// Assign indexing
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lab.alms.at(z).lut_bels.at(i) = bel;
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arch->bels.at(bel).lab_data.lab = lab_idx;
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arch->bels.at(bel).lab_data.alm = z;
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arch->bels.at(bel).lab_data.idx = i;
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}
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// Create the control set and E/F selection - which is per pair of FF
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std::array<WireId, 2> sel_clk, sel_ena, sel_aclr, sel_ef;
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for (int i = 0; i < 2; i++) {
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// Wires
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sel_clk[i] = arch->add_wire(x, y, arch->id(stringf("CLK%c[%d]", i ? 'B' : 'T', z)));
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sel_ena[i] = arch->add_wire(x, y, arch->id(stringf("ENA%c[%d]", i ? 'B' : 'T', z)));
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sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z)));
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sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z)));
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// Muxes - three CLK/ENA per LAB, two ACLR
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for (int j = 0; j < 3; i++) {
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arch->add_pip(lab.clk_wires[j], sel_clk[i]);
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arch->add_pip(lab.ena_wires[j], sel_ena[i]);
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if (j < 2)
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arch->add_pip(lab.aclr_wires[j], sel_aclr[i]);
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}
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// E/F pips
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arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::E1 : CycloneV::E0), sel_ef[i]);
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arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::F1 : CycloneV::F0), sel_ef[i]);
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}
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// Create the flipflops and associated routing
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const CycloneV::port_type_t outputs[4] = {CycloneV::FFT0, CycloneV::FFT1, CycloneV::FFB0, CycloneV::FFB1};
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const CycloneV::port_type_t l_outputs[4] = {CycloneV::FFT1L, CycloneV::FFB1L};
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for (int i = 0; i < 4; i++) {
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// FF input, selected by *PKREG*
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WireId comb_out = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", (z * 2) + (i / 2))));
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WireId ff_in = arch->add_wire(x, y, arch->id(stringf("FFIN[%d]", (z * 4) + i)));
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arch->add_pip(comb_out, ff_in);
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arch->add_pip(sel_ef[i / 2], ff_in);
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// FF bel
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BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_FF%d", z, i)), id_MISTRAL_FF);
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arch->add_bel_pin(bel, id_CLK, PORT_IN, sel_clk[i / 2]);
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arch->add_bel_pin(bel, id_ENA, PORT_IN, sel_ena[i / 2]);
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arch->add_bel_pin(bel, id_ACLR, PORT_IN, sel_aclr[i / 2]);
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arch->add_bel_pin(bel, id_SCLR, PORT_IN, lab.sclr_wire);
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arch->add_bel_pin(bel, id_SLOAD, PORT_IN, lab.sload_wire);
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arch->add_bel_pin(bel, id_DATAIN, PORT_IN, ff_in);
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arch->add_bel_pin(bel, id_SDATA, PORT_IN, sel_ef[i / 2]);
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// FF output
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WireId ff_out = arch->add_wire(x, y, arch->id(stringf("FFOUT[%d]", (z * 4) + i)));
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arch->add_bel_pin(bel, id_Q, PORT_OUT, ff_out);
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// Output mux (*DFF*)
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WireId out = arch->get_port(CycloneV::LAB, x, y, z, outputs[i]);
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arch->add_pip(ff_out, out);
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arch->add_pip(comb_out, out);
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// 'L' output mux where applicable
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if (i == 1 || i == 3) {
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WireId l_out = arch->get_port(CycloneV::LAB, x, y, z, l_outputs[i / 2]);
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arch->add_pip(ff_out, l_out);
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arch->add_pip(comb_out, l_out);
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}
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lab.alms.at(z).ff_bels.at(i) = bel;
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arch->bels.at(bel).lab_data.lab = lab_idx;
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arch->bels.at(bel).lab_data.alm = z;
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arch->bels.at(bel).lab_data.idx = i;
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}
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}
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} // namespace
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void Arch::create_lab(int x, int y)
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{
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uint32_t lab_idx = labs.size();
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labs.emplace_back();
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auto &lab = labs.back();
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// Create common control set configuration. This is actually a subset of what's possible, but errs on the side of
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// caution due to incomplete documentation
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// Clocks - hardcode to CLKA choices, as both CLKA and CLKB coming from general routing causes unexpected
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// permutations
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for (int i = 0; i < 3; i++) {
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lab.clk_wires[i] = add_wire(x, y, id(stringf("CLK%d", i)));
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add_pip(get_port(CycloneV::LAB, x, y, -1, CycloneV::CLKIN, 0), lab.clk_wires[i]); // dedicated routing
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add_pip(get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 0), lab.clk_wires[i]); // general routing
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}
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// Enables - while it looks from the config like there are choices for these, it seems like EN0_SEL actually selects
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// SCLR not ENA0 and EN1_SEL actually selects SLOAD?
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lab.ena_wires[0] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 2);
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lab.ena_wires[1] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 3);
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lab.ena_wires[2] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 0);
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// ACLRs - only consider general routing for now
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lab.aclr_wires[0] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 3);
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lab.aclr_wires[1] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 2);
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// SCLR and SLOAD - as above it seems like these might be selectable using the "EN*_SEL" bits but play it safe for
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// now
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lab.sclr_wire = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 3);
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lab.sload_wire = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 1);
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for (int i = 0; i < 10; i++) {
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create_alm(this, x, y, i, lab_idx);
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}
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}
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NEXTPNR_NAMESPACE_END
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