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mistral: Fix EF_SEL and BTO_DIS

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-14 23:08:32 +01:00
parent 8bc9732d49
commit 87ebada258
2 changed files with 5 additions and 4 deletions
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6
mistral/bitstream.cc
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@ -241,9 +241,9 @@ struct MistralBitgen
cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::ARITH_SEL, alm, CycloneV::ADDER);
// The carry in/out enable bits
if (is_carry && alm == 0 && !luts[0]->combInfo.carry_start)
cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::TTO_DIS, alm, true);
cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::TTO_DIS, 0, true);
if (is_carry && alm == 5)
cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, alm, true);
cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, 0, true);
// Flipflop configuration
const std::array<CycloneV::bmux_type_t, 2> ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL};
// This isn't a typo; the *PKREG* bits really are mirrored.
@ -263,7 +263,7 @@ struct MistralBitgen
for (int i = 0; i < 2; i++) {
// EF selection mux
if (ctx->wires_connected(ctx->getBelPinWire(alm_data.lut_bels[i], i ? id_F1 : id_F0), alm_data.sel_ef[i]))
if (ctx->wires_connected(ctx->getBelPinWire(alm_data.lut_bels[i], i ? id_F0 : id_F1), alm_data.sel_ef[i]))
cv->bmux_m_set(CycloneV::LAB, pos, ef_sel[i], alm, CycloneV::bmux_type_t::F);
}

3
mistral/lab.cc
View File

@ -104,8 +104,9 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
arch->add_pip(lab.aclr_wires[j], alm.sel_aclr[i]);
}
// E/F pips
// Note that the F choice is mirrored, F from the other half is picked
arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::E1 : CycloneV::E0), alm.sel_ef[i]);
arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::F1 : CycloneV::F0), alm.sel_ef[i]);
arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::F0 : CycloneV::F1), alm.sel_ef[i]);
}
// Create the flipflops and associated routing