From 883f27480274cd6385bce118dc31d260ec9ae832 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 10 Mar 2022 10:28:57 +0000
Subject: [PATCH] mistral: M10K initialisation support

---
 mistral/bitstream.cc | 19 +++++++++++++++++--
 mistral/constids.inc |  1 +
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 6a2c3825..c5105008 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -153,9 +153,24 @@ struct MistralBitgen
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0);
 
-        // Note for future us: the RAM init contents are inverted.
+        auto permute_init = [](int64_t init) -> int64_t {
+            const int permutation[40] = {0, 20, 10, 30, 1, 21, 11, 31, 2, 22, 12, 32, 3, 23, 13, 33, 4, 24, 14, 34,
+                                         5, 25, 15, 35, 6, 26, 16, 36, 7, 27, 17, 37, 8, 28, 18, 38, 9, 29, 19, 39};
+
+            int64_t output = 0;
+            for (int bit = 0; bit < 40; bit++)
+                output |= ((init >> permutation[bit]) & 1) << bit;
+            return ~output; // RAM init is inverted.
+        };
+
+        Property init;
+        if (ci->params.count(id_INIT) == 0) {
+            init = Property{0, 10240};
+        } else {
+            init = ci->params.at(id_INIT);
+        }
         for (int bi = 0; bi < 256; bi++)
-            cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff);
+            cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, permute_init(init.extract(bi * 40, 40).as_int64()));
     }
 
     void write_cells()
diff --git a/mistral/constids.inc b/mistral/constids.inc
index 262fd12a..754a96b3 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -100,6 +100,7 @@ X(cyclonev_oscillator)
 X(cyclonev_hps_interface_mpu_general_purpose)
 
 X(MISTRAL_M10K)
+X(INIT)
 X(ADDRSTALLA)
 X(ADDRSTALLB)
 X(CFG_ABITS)