machxo2: Add basic bitstream generation for PIC tiles and I/O.
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@ -116,6 +116,26 @@ std::string intstr_or_default(const std::unordered_map<IdString, Property> &ct,
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}
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}
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};
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};
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// Get the PIC tile corresponding to a PIO bel
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static std::string get_pic_tile(Context *ctx, BelId bel)
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{
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static const std::set<std::string> pio_l = {"PIC_L0", "PIC_LS0", "PIC_L0_VREF3"};
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static const std::set<std::string> pio_r = {"PIC_R0", "PIC_RS0"};
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std::string pio_name = ctx->tileInfo(bel)->bel_data[bel.index].name.get();
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if (bel.location.y == 0) {
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return ctx->getTileByTypeAndLocation(0, bel.location.x, "PIC_T0");
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} else if (bel.location.y == ctx->chip_info->height - 1) {
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return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, "PIC_B0");
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} else if (bel.location.x == 0) {
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return ctx->getTileByTypeAndLocation(bel.location.y, 0, pio_l);
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} else if (bel.location.x == ctx->chip_info->width - 1) {
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return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, pio_r);
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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}
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void write_bitstream(Context *ctx, std::string text_config_file)
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void write_bitstream(Context *ctx, std::string text_config_file)
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{
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{
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ChipConfig cc;
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ChipConfig cc;
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@ -174,6 +194,12 @@ void write_bitstream(Context *ctx, std::string text_config_file)
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str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
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str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
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cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
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cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
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str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
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str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
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} else if (ci->type == ctx->id("FACADE_IO")) {
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std::string pio = ctx->tileInfo(bel)->bel_data[bel.index].name.get();
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std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
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std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
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std::string pic_tile = get_pic_tile(ctx, bel);
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cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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}
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}
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}
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}
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