diff --git a/nexus/arch.h b/nexus/arch.h index f787c2b3..29acc5f5 100644 --- a/nexus/arch.h +++ b/nexus/arch.h @@ -1271,6 +1271,18 @@ struct Arch : BaseCtx int wire = pip_data(pip).to_wire; return db->loctypes[chip_info->grid[pip.tile].loc_type].wires[wire].name; } + + // ------------------------------------------------- + + // Get a map cell type -> pins that can be inverted + void get_invertible_pins(std::unordered_map> &pins) const; + // Get a map cell -> pin -> value _it takes_ if disconnected + void get_pins_floating_value(std::unordered_map> &pins) const; + // Get a map cell -> pin -> value _it must be connected to_ if disconnected + // Default value for all pins, if not specified is 0 + void + get_pins_default_value(std::unordered_map> &pins) const; + // ------------------------------------------------- NeighWireRange neigh_wire_range(WireId wire) const diff --git a/nexus/pack.cc b/nexus/pack.cc index 5a18f6d4..c1e3664f 100644 --- a/nexus/pack.cc +++ b/nexus/pack.cc @@ -40,6 +40,7 @@ struct NexusPacker std::unordered_map param_xform; std::vector> set_attrs; std::vector> set_params; + std::vector> default_params; }; void xform_cell(const std::unordered_map &rules, CellInfo *ci) @@ -87,6 +88,10 @@ struct NexusPacker for (auto &attr : rule.set_attrs) ci->attrs[attr.first] = attr.second; + for (auto ¶m : rule.default_params) + if (!ci->params.count(param.first)) + ci->params[param.first] = param.second; + for (auto ¶m : rule.set_params) ci->params[param.first] = param.second; } @@ -134,6 +139,11 @@ struct NexusPacker ff_rules[type].port_xform[id_D] = id_M; // will be rerouted to DI later if applicable ff_rules[type].port_xform[id_SP] = id_CE; ff_rules[type].port_xform[id_Q] = id_Q; + + ff_rules[id_FD1P3BX].default_params.emplace_back(id_CLKMUX, std::string("CLK")); + ff_rules[id_FD1P3BX].default_params.emplace_back(id_CEMUX, std::string("CE")); + ff_rules[id_FD1P3BX].default_params.emplace_back(id_LSRMUX, std::string("LSR")); + ff_rules[id_FD1P3BX].set_params.emplace_back(id_LSRMODE, std::string("LSR")); } // Async preload ff_rules[id_FD1P3BX].set_params.emplace_back(id_SRMODE, std::string("ASYNC")); diff --git a/nexus/pins.cc b/nexus/pins.cc new file mode 100644 index 00000000..5627f557 --- /dev/null +++ b/nexus/pins.cc @@ -0,0 +1,53 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2020 David Shah + * + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "nextpnr.h" + +NEXTPNR_NAMESPACE_BEGIN + +void Arch::get_invertible_pins(std::unordered_map> &pins) const +{ + pins[id_OXIDE_FF] = {id_CLK, id_LSR, id_CE}; + pins[id_RAMW] = {id_WCK}; + pins[id_SEIO18_CORE] = {id_T}; + pins[id_SEIO33_CORE] = {id_T}; +} + +void Arch::get_pins_floating_value(std::unordered_map> &pins) const +{ + pins[id_OXIDE_COMB] = {{id_A, true}, {id_B, true}, {id_C, true}, {id_D, true}, {id_SEL, true}}; + pins[id_OXIDE_FF] = {{id_CLK, false}, {id_LSR, true}, {id_CE, true}}; + pins[id_SEIO18_CORE] = {{id_T, true}}; + pins[id_SEIO33_CORE] = {{id_T, true}}; +} + +void Arch::get_pins_default_value( + std::unordered_map> &pins) const +{ + pins[id_OXIDE_COMB] = {{id_A, Property::S1}, {id_B, Property::S1}, {id_C, Property::S1}, + {id_D, Property::S1}, {id_SEL, Property::S1}, {id_WAD0, Property::Sx}, + {id_WAD1, Property::Sx}, {id_WAD2, Property::Sx}, {id_WAD3, Property::Sx}, + {id_WCK, Property::Sx}, {id_WRE, Property::Sx}, {id_WD, Property::Sx}}; + pins[id_OXIDE_FF] = {{id_CE, Property::S1}, {id_DI, Property::Sx}}; + pins[id_SEIO18_CORE] = {{id_T, Property::S1}}; + pins[id_SEIO33_CORE] = {{id_T, Property::S1}}; +} + +NEXTPNR_NAMESPACE_END \ No newline at end of file