ecp5: Adding cell definitions
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah
parent
b55142cbf1
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889e1fc19f
124
ecp5/cells.cc
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124
ecp5/cells.cc
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "cells.h"
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#include "log.h"
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#include "util.h"
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#include "design_utils.h"
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NEXTPNR_NAMESPACE_BEGIN
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void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
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{
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IdString id = ctx->id(name);
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cell->ports[id] = PortInfo{id, nullptr, dir};
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}
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std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name = "") {
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static int auto_idx = 0;
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std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
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if (name.empty()) {
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new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
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} else {
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new_cell->name = ctx->id(name);
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}
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new_cell->type = type;
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if (type == ctx->id("TRELLIS_LC")) {
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new_cell->params[ctx->id("MODE")] = "LOGIC";
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new_cell->params[ctx->id("GSR")] = "DISABLED";
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new_cell->params[ctx->id("SRMODE")] = "LSR_OVER_CE";
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new_cell->params[ctx->id("CEMUX")] = "1";
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new_cell->params[ctx->id("CLKMUX")] = "CLK";
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new_cell->params[ctx->id("LSRMUX")] = "LSR";
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new_cell->params[ctx->id("LUT0_INITVAL")] = "0";
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new_cell->params[ctx->id("LUT1_INITVAL")] = "0";
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new_cell->params[ctx->id("REG0_SD")] = "0";
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new_cell->params[ctx->id("REG1_SD")] = "0";
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new_cell->params[ctx->id("REG0_REGSET")] = "RESET";
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new_cell->params[ctx->id("REG1_REGSET")] = "RESET";
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new_cell->params[ctx->id("CCU2_INJECT1_0")] = "NO";
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new_cell->params[ctx->id("CCU2_INJECT1_1")] = "NO";
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new_cell->params[ctx->id("WREMUX")] = "WRE";
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add_port(ctx, new_cell.get(), "A0", PORT_IN);
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add_port(ctx, new_cell.get(), "B0", PORT_IN);
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add_port(ctx, new_cell.get(), "C0", PORT_IN);
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add_port(ctx, new_cell.get(), "D0", PORT_IN);
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add_port(ctx, new_cell.get(), "A1", PORT_IN);
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add_port(ctx, new_cell.get(), "B1", PORT_IN);
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add_port(ctx, new_cell.get(), "C1", PORT_IN);
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add_port(ctx, new_cell.get(), "D1", PORT_IN);
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add_port(ctx, new_cell.get(), "M0", PORT_IN);
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add_port(ctx, new_cell.get(), "M1", PORT_IN);
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add_port(ctx, new_cell.get(), "FCI", PORT_IN);
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add_port(ctx, new_cell.get(), "FXA", PORT_IN);
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add_port(ctx, new_cell.get(), "FXB", PORT_IN);
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add_port(ctx, new_cell.get(), "CLK", PORT_IN);
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add_port(ctx, new_cell.get(), "LSR", PORT_IN);
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add_port(ctx, new_cell.get(), "CE", PORT_IN);
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add_port(ctx, new_cell.get(), "DI0", PORT_IN);
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add_port(ctx, new_cell.get(), "DI1", PORT_IN);
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add_port(ctx, new_cell.get(), "WD0", PORT_IN);
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add_port(ctx, new_cell.get(), "WD1", PORT_IN);
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add_port(ctx, new_cell.get(), "WAD0", PORT_IN);
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add_port(ctx, new_cell.get(), "WAD1", PORT_IN);
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add_port(ctx, new_cell.get(), "WAD2", PORT_IN);
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add_port(ctx, new_cell.get(), "WAD3", PORT_IN);
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add_port(ctx, new_cell.get(), "WRE", PORT_IN);
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add_port(ctx, new_cell.get(), "WCK", PORT_IN);
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add_port(ctx, new_cell.get(), "F0", PORT_OUT);
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add_port(ctx, new_cell.get(), "Q0", PORT_OUT);
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add_port(ctx, new_cell.get(), "F1", PORT_OUT);
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add_port(ctx, new_cell.get(), "Q1", PORT_OUT);
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add_port(ctx, new_cell.get(), "FCO", PORT_OUT);
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add_port(ctx, new_cell.get(), "OFX0", PORT_OUT);
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add_port(ctx, new_cell.get(), "OFX1", PORT_OUT);
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add_port(ctx, new_cell.get(), "WDO0", PORT_OUT);
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add_port(ctx, new_cell.get(), "WDO1", PORT_OUT);
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add_port(ctx, new_cell.get(), "WDO2", PORT_OUT);
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add_port(ctx, new_cell.get(), "WDO3", PORT_OUT);
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add_port(ctx, new_cell.get(), "WADO0", PORT_OUT);
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add_port(ctx, new_cell.get(), "WADO1", PORT_OUT);
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add_port(ctx, new_cell.get(), "WADO2", PORT_OUT);
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add_port(ctx, new_cell.get(), "WADO3", PORT_OUT);
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} else if (type == ctx->id("TRELLIS_IO")) {
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new_cell->params[ctx->id("DIR")] = "INPUT";
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new_cell->attrs[ctx->id("IO_TYPE")] = "LVCMOS33";
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add_port(ctx, new_cell.get(), "B", PORT_INOUT);
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add_port(ctx, new_cell.get(), "I", PORT_IN);
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add_port(ctx, new_cell.get(), "T", PORT_IN);
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add_port(ctx, new_cell.get(), "O", PORT_OUT);
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} else {
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log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
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}
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return new_cell;
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}
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NEXTPNR_NAMESPACE_END
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59
ecp5/cells.h
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59
ecp5/cells.h
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@ -0,0 +1,59 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef ECP5_CELLS_H
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#define ECP5_CELLS_H
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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// Create a standard ECP5 cell and return it
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// Name will be automatically assigned if not specified
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std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name = "");
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// Return true if a cell is a LUT
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inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell)
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{ return cell->type == ctx->id("LUT4"); }
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// Return true if a cell is a flipflop
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inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
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{
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return cell->type == ctx->id("TRELLIS_FF");
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}
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inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell)
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{ return cell->type == ctx->id("CCU2C"); }
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inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell)
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{ return cell->type == ctx->id("TRELLIS_LC"); }
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inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell)
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{ return cell->type == ctx->id("TRELLIS_DPR16X4"); }
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inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell)
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{ return cell->type == ctx->id("PFUMX"); }
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inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell)
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{ return cell->type == ctx->id("L6MUX21"); }
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NEXTPNR_NAMESPACE_END
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#endif
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