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Use hashlib in frontend, where possible

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-06-02 11:44:57 +01:00
parent eca1a4cee4
commit 897e2c2fdc
1 changed files with 6 additions and 6 deletions
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12
frontend/frontend_base.h
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@ -118,7 +118,7 @@ struct ModuleInfo
{ {
bool is_top = false, is_blackbox = false, is_whitebox = false; bool is_top = false, is_blackbox = false, is_whitebox = false;
inline bool is_box() const { return is_blackbox || is_whitebox; } inline bool is_box() const { return is_blackbox || is_whitebox; }
std::unordered_set<IdString> instantiated_celltypes; pool<IdString> instantiated_celltypes;
}; };
template <typename FrontendType> struct GenericFrontend template <typename FrontendType> struct GenericFrontend
@ -148,7 +148,7 @@ template <typename FrontendType> struct GenericFrontend
using netname_dat_t = typename FrontendType::NetnameDataType; using netname_dat_t = typename FrontendType::NetnameDataType;
using bitvector_t = typename FrontendType::BitVectorDataType; using bitvector_t = typename FrontendType::BitVectorDataType;
std::unordered_map<IdString, ModuleInfo> mods; dict<IdString, ModuleInfo> mods;
std::unordered_map<IdString, const mod_dat_t> mod_refs; std::unordered_map<IdString, const mod_dat_t> mod_refs;
IdString top; IdString top;
@ -196,7 +196,7 @@ template <typename FrontendType> struct GenericFrontend
} }
// Finally, attempt to autodetect the top module using hierarchy // Finally, attempt to autodetect the top module using hierarchy
// (a module that is not a box and is not used as a cell by any other module) // (a module that is not a box and is not used as a cell by any other module)
std::unordered_set<IdString> candidate_top; pool<IdString> candidate_top;
for (auto &mod : mods) for (auto &mod : mods)
if (!mod.second.is_box()) if (!mod.second.is_box())
candidate_top.insert(mod.first); candidate_top.insert(mod.first);
@ -207,7 +207,7 @@ template <typename FrontendType> struct GenericFrontend
if (candidate_top.size() == 0) if (candidate_top.size() == 0)
log_info("No candidate top level modules.\n"); log_info("No candidate top level modules.\n");
else else
for (auto ctp : sorted(candidate_top)) for (auto ctp : candidate_top)
log_info("Candidate top module: '%s'\n", ctx->nameOf(ctp)); log_info("Candidate top module: '%s'\n", ctx->nameOf(ctp));
log_error("Failed to autodetect top module, please specify using --top.\n"); log_error("Failed to autodetect top module, please specify using --top.\n");
} }
@ -256,7 +256,7 @@ template <typename FrontendType> struct GenericFrontend
index_to_net_flatindex.resize(idx + 1, -1); index_to_net_flatindex.resize(idx + 1, -1);
return index_to_net_flatindex.at(idx); return index_to_net_flatindex.at(idx);
} }
std::unordered_map<IdString, std::vector<int>> port_to_bus; dict<IdString, std::vector<int>> port_to_bus;
// All of the names given to a net // All of the names given to a net
std::vector<std::vector<std::string>> net_names; std::vector<std::vector<std::string>> net_names;
}; };
@ -453,7 +453,7 @@ template <typename FrontendType> struct GenericFrontend
CellInfo *ci = ctx->createCell(inst_name, ctx->id(impl.get_cell_type(cd))); CellInfo *ci = ctx->createCell(inst_name, ctx->id(impl.get_cell_type(cd)));
ci->hierpath = m.path; ci->hierpath = m.path;
// Import port directions // Import port directions
std::unordered_map<IdString, PortType> port_dirs; dict<IdString, PortType> port_dirs;
impl.foreach_port_dir(cd, [&](const std::string &port, PortType dir) { port_dirs[ctx->id(port)] = dir; }); impl.foreach_port_dir(cd, [&](const std::string &port, PortType dir) { port_dirs[ctx->id(port)] = dir; });
// Import port connectivity // Import port connectivity
impl.foreach_port_conn(cd, [&](const std::string &name, const bitvector_t &bits) { impl.foreach_port_conn(cd, [&](const std::string &name, const bitvector_t &bits) {