machxo2: Stub valid BEL functions with comment. Place phase segfaults.
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@ -382,12 +382,17 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
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bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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{
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{
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return false;
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// FIXME: Unlike ECP5, SLICEs in a given tile do not share a clock, so
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// any SLICE Cell is valid for any BEL, even if some cells are already
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// bound to BELs in the tile. However, this may need to be filled in once
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// more than one LUT4 and DFF type is supported.
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return true;
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}
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}
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bool Arch::isBelLocationValid(BelId bel) const
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bool Arch::isBelLocationValid(BelId bel) const
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{
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{
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return false;
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// FIXME: Same deal as isValidBelForCell.
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return true;
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}
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}
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#ifdef WITH_HEAP
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#ifdef WITH_HEAP
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