Merge pull request #567 from litghost/initial_fpga_interchange
Initial FPGA interchange arch
This commit is contained in:
David Shah
GitHub
commit
8b4163b77c
1
.gitignore
vendored
1
.gitignore
vendored
@ -4,6 +4,7 @@
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/nextpnr-ice40*
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/nextpnr-ecp5*
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/nextpnr-nexus*
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/nextpnr-fpga_interchange*
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cmake-build-*/
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Makefile
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cmake_install.cmake
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@ -66,9 +66,9 @@ endif()
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set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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# List of families to build
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set(FAMILIES generic ice40 ecp5 nexus gowin)
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set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(EXPERIMENTAL_FAMILIES nexus gowin)
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set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange)
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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@ -32,6 +32,7 @@ NPNR_PACKED_STRUCT(template <typename T> struct RelSlice {
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const T *end() const { return get() + length; }
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const size_t size() const { return length; }
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const ptrdiff_t ssize() const { return length; }
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const T &operator*() const { return *(get()); }
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162
fpga_interchange/README.md
Normal file
162
fpga_interchange/README.md
Normal file
@ -0,0 +1,162 @@
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## FPGA interchange nextpnr architecture
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This nextpnr architecture is a meta architecture that in theory will implement
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any architecture that emits a complete FPGA interchange device database.
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### FPGA interchange
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The FPGA interchange is a set of file formats intended to describe any modern
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island based FPGA. It consists of three primary file formats:
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- Device database
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- This is a description of a particular FPGA fabric. This description
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includes placement locations, placement constraints and a complete
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description of the routing fabric.
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- This file will also include timing information once added.
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- Logical netlist
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- This is the output of a synthesis tool. This is equivalent to the
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Yosys JSON format, EDIF, or eblif.
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- As part of future nextpnr development, a frontend will be added that
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takes this format as input.
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- Physical netlist
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- This is the output of a place and route tool. It can describe a clustered
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design, a partially or fully placed design, and a partially or fully
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routed design.
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### Current status
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This architecture implementation can be compiled in conjunction with a FPGA
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interchange device database, and the outputs from
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`fpga_interchange.nextpnr_emit`, which is part of the
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[python-fpga-interchange](https://github.com/SymbiFlow/python-fpga-interchange/)
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library.
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The current implementation is missing essential features for place and route.
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As these features are added, this implementation will become more useful.
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- [ ] Placement constraints are unimplemented, meaning invalid or unroutable
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designs can be generated from the placer.
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- [ ] Logical netlist macro expansion is not implemented, meaning that any
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macro primitives are unplaceable. Common macro primitives examples are
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differential IO buffers (IBUFDS) and some LUT RAM (e.g. RAM64X1D).
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- [ ] Cell -> BEL pin mapping is not in place, meaning any primitives that
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have different BEL pins with respect to their cell pins will not be
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routable.
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- [ ] Nextpnr only allows for cell -> BEL pin maps that are 1 to 1. The
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FPGA interchange accommodates cell -> BEL pin maps that include 1 to
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many relationships for sinks. A common primitives that uses 1 to many
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maps are the RAMB18E1.
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- [ ] The router lookahead is missing, meaning that router runtime
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performance will be terrible.
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- [ ] Physical netlist backend is missing, so even if
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`nextpnr-fpga_interchange` completes successfully, there is no way to
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generate output that can be consumed by downstream tools.
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- [ ] XDC parsing and port constraints are unimplemented, so IO pins cannot
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be fixed. The chipdb BBA output is also missing package pin data, so
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only site constraints are currently possible. Eventually the chipdb BBA
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should also include package pin data to allow for ports to be bound to
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package pins.
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- [ ] The routing graph that is currently emitted does not have ground and
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VCC networks, so all signals must currently be tied to an IO signal.
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Site pins being tied to constants also needs handling so that site
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local inverters are used rather than routing signals suboptimally.
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- [ ] Pseudo pips (e.g. pips that consume BELs and or site resources) should
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block their respective resources. This effects designs that have some
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routing in place before placement.
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- [ ] Pseudo site pips (e.g. site pips that route through BELs) should block
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their respective resources. Without this, using some pseudo site pips
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could result in invalid placements.
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- [ ] Timing information is missing from the FPGA interchange device
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database, so it is also currently missing from the FPGA interchange
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architecture. Once timing information is added to the device database
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schema, it needs to be added to the architecture.
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#### FPGA interchange fabrics
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Currently only Xilinx 7-series, UltraScale and UltraScale+ fabrics have a
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device database generator, via [RapidWright](https://github.com/Xilinx/RapidWright).
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##### Artix 35T example
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Download RapidWright and generate the device database.
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```
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# FIXME: Use main branch once interchange branch is merged.
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git clone -b interchange https://github.com/Xilinx/RapidWright.git
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cd RapidWright
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make update_jars
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# FIXME: Current RapidWright jars generate database with duplicate PIPs
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# https://github.com/Xilinx/RapidWright/issues/127
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# Remove this wget once the latest RapidWright JAR is published.
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wget https://github.com/Xilinx/RapidWright/releases/download/v2020.2.1-beta/rapidwright-api-lib-2020.2.1_update1.jar
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mv rapidwright-api-lib-2020.2.1_update1.jar jars/rapidwright-api-lib-2020.2.0.jar
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./scripts/invoke_rapidwright.sh com.xilinx.rapidwright.interchange.DeviceResourcesExample xc7a35tcpg236-1
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export RAPIDWRIGHT_PATH=$(pwd)
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export INTERCHANGE_DIR=$(pwd)/interchange
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```
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Install python FPGA interchange library.
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```
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git clone https://github.com/SymbiFlow/python-fpga-interchange.git
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cd python-fpga-interchange
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pip install -r requirements.txt
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```
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Patch device database with cell constraints and LUT annotations:
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```
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python3 -mfpga_interchange.patch \
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--schema_dir ${INTERCHANGE_DIR} \
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--schema device \
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--patch_path constraints \
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--patch_format yaml \
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${RAPIDWRIGHT_PATH}/xc7a35tcpg236-1.device \
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test_data/series7_constraints.yaml \
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xc7a35tcpg236-1_constraints.device
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python3 -mfpga_interchange.patch \
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--schema_dir ${INTERCHANGE_DIR} \
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--schema device \
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--patch_path lutDefinitions \
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--patch_format yaml \
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xc7a35tcpg236-1_constraints.device \
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test_data/series7_luts.yaml \
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xc7a35tcpg236-1_constraints_luts.device
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```
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Generate nextpnr BBA and constids.inc from device database:
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```
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python3 -mfpga_interchange.nextpnr_emit \
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--schema_dir ${INTERCHANGE_DIR} \
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--output_dir ${NEXTPNR_DIR}/fpga_interchange/ \
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--device xc7a35tcpg236-1_constraints_luts.device
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```
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Build nextpnr:
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```
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cd ${NEXTPNR_DIR}
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cmake -DARCH=fpga_interchange .
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make -j
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```
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Compile generated BBA:
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```
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bba/bbasm -l fpga_interchange/chipdb.bba fpga_interchange/chipdb.bin
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```
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Run nextpnr archcheck:
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```
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./nextpnr-fpga_interchange --chipdb fpga_interchange/chipdb.bin --test
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```
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Once nextpnr can complete the place and route task and output the physical
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netlist, RapidWright can be used to generate a DCP suitable for bitstream
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output and DRC checks.
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```
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${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh \
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com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \
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<logical netlist file> <physical netlist file> <XDC file> <output DCP>
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```
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578
fpga_interchange/arch.cc
Normal file
578
fpga_interchange/arch.cc
Normal file
@ -0,0 +1,578 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
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* Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
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* Copyright (C) 2021 Symbiflow Authors
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <boost/algorithm/string.hpp>
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#include <boost/range/adaptor/reversed.hpp>
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#include <cmath>
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#include <cstring>
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#include <queue>
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "router2.h"
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#include "timing.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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static std::pair<std::string, std::string> split_identifier_name_dot(const std::string &name)
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{
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size_t first_dot = name.find('.');
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NPNR_ASSERT(first_dot != std::string::npos);
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return std::make_pair(name.substr(0, first_dot), name.substr(first_dot + 1));
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};
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx) {}
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// -----------------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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Arch::Arch(ArchArgs args) : args(args)
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{
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try {
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blob_file.open(args.chipdb);
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if (args.chipdb.empty() || !blob_file.is_open())
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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const char *blob = reinterpret_cast<const char *>(blob_file.data());
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(blob));
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} catch (...) {
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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}
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// Read strings from constids into IdString database, checking that list
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// is unique and matches expected constid value.
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int id = 1;
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for (const auto &constid : *chip_info->constids) {
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IdString::initialize_add(this, constid.get(), id++);
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}
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tileStatus.resize(chip_info->tiles.size());
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for (int i = 0; i < chip_info->tiles.ssize(); i++) {
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tileStatus[i].boundcells.resize(chip_info->tile_types[chip_info->tiles[i].type].bel_data.size());
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}
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// Sanity check cell name ids.
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const CellMapPOD &cell_map = *chip_info->cell_map;
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int32_t first_cell_id = cell_map.cell_names[0];
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for (int32_t i = 0; i < cell_map.cell_names.ssize(); ++i) {
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log_assert(cell_map.cell_names[i] == i + first_cell_id);
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}
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName() const { return chip_info->name.get(); }
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// -----------------------------------------------------------------------
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IdString Arch::archArgsToId(ArchArgs args) const { return IdString(); }
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// -----------------------------------------------------------------------
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void Arch::setup_byname() const
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{
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if (tile_by_name.empty()) {
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for (int i = 0; i < chip_info->tiles.ssize(); i++) {
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tile_by_name[id(chip_info->tiles[i].name.get())] = i;
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}
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}
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if (site_by_name.empty()) {
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for (int i = 0; i < chip_info->tiles.ssize(); i++) {
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auto &tile = chip_info->tiles[i];
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auto &tile_type = chip_info->tile_types[tile.type];
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for (int j = 0; j < tile_type.number_sites; j++) {
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auto &site = chip_info->sites[tile.sites[j]];
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site_by_name[id(site.name.get())] = std::make_pair(i, j);
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}
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}
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}
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}
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BelId Arch::getBelByName(IdStringList name) const
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{
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BelId ret;
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if (name.ids.size() != 2) {
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return BelId();
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}
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setup_byname();
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int tile, site;
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std::tie(tile, site) = site_by_name.at(name.ids[0]);
|
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auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
|
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IdString belname = name.ids[1];
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for (int i = 0; i < tile_info.bel_data.ssize(); i++) {
|
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if (tile_info.bel_data[i].site == site && tile_info.bel_data[i].name == belname.index) {
|
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ret.tile = tile;
|
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ret.index = i;
|
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break;
|
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}
|
||||
}
|
||||
|
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return ret;
|
||||
}
|
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|
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BelRange Arch::getBelsByTile(int x, int y) const
|
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{
|
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BelRange br;
|
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|
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br.b.cursor_tile = get_tile_index(x, y);
|
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br.e.cursor_tile = br.b.cursor_tile;
|
||||
br.b.cursor_index = 0;
|
||||
br.e.cursor_index = chip_info->tile_types[chip_info->tiles[br.b.cursor_tile].type].bel_data.size();
|
||||
br.b.chip = chip_info;
|
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br.e.chip = chip_info;
|
||||
|
||||
if (br.b != br.e) {
|
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++br.e;
|
||||
}
|
||||
return br;
|
||||
}
|
||||
|
||||
WireId Arch::getBelPinWire(BelId bel, IdString pin) const
|
||||
{
|
||||
NPNR_ASSERT(bel != BelId());
|
||||
|
||||
int pin_index = get_bel_pin_index(bel, pin);
|
||||
|
||||
auto &bel_data = bel_info(chip_info, bel);
|
||||
NPNR_ASSERT(pin_index >= 0 && pin_index < bel_data.num_bel_wires);
|
||||
|
||||
const int32_t *wires = bel_data.wires.get();
|
||||
int32_t wire_index = wires[pin_index];
|
||||
if (wire_index < 0) {
|
||||
// This BEL pin is not connected.
|
||||
return WireId();
|
||||
} else {
|
||||
return canonical_wire(chip_info, bel.tile, wire_index);
|
||||
}
|
||||
}
|
||||
|
||||
PortType Arch::getBelPinType(BelId bel, IdString pin) const
|
||||
{
|
||||
NPNR_ASSERT(bel != BelId());
|
||||
|
||||
int pin_index = get_bel_pin_index(bel, pin);
|
||||
auto &bel_data = bel_info(chip_info, bel);
|
||||
NPNR_ASSERT(pin_index >= 0 && pin_index < bel_data.num_bel_wires);
|
||||
const int32_t *types = bel_data.types.get();
|
||||
return PortType(types[pin_index]);
|
||||
}
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
WireId Arch::getWireByName(IdStringList name) const
|
||||
{
|
||||
WireId ret;
|
||||
if (name.ids.size() != 2) {
|
||||
return WireId();
|
||||
}
|
||||
|
||||
setup_byname();
|
||||
|
||||
auto iter = site_by_name.find(name.ids[0]);
|
||||
if (iter != site_by_name.end()) {
|
||||
int tile;
|
||||
int site;
|
||||
std::tie(tile, site) = iter->second;
|
||||
auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
|
||||
IdString wirename = name.ids[1];
|
||||
for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
|
||||
if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == wirename.index) {
|
||||
ret.tile = tile;
|
||||
ret.index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
int tile = tile_by_name.at(name.ids[0]);
|
||||
auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
|
||||
IdString wirename = name.ids[1];
|
||||
for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
|
||||
if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == wirename.index) {
|
||||
int32_t node = chip_info->tiles[tile].tile_wire_to_node[i];
|
||||
if (node == -1) {
|
||||
// Not a nodal wire
|
||||
ret.tile = tile;
|
||||
ret.index = i;
|
||||
} else {
|
||||
// Is a nodal wire, set tile to -1
|
||||
ret.tile = -1;
|
||||
ret.index = node;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
IdString Arch::getWireType(WireId wire) const { return id(""); }
|
||||
std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
PipId Arch::getPipByName(IdStringList name) const
|
||||
{
|
||||
// PIP name structure:
|
||||
// Tile PIP: <tile name>/<source wire name>.<destination wire name>
|
||||
// Site PIP: <site name>/<bel name>/<input bel pin name>
|
||||
// Site pin: <site name>/<bel name>
|
||||
// Psuedo site PIP: <site name>/<source wire name>.<destination wire name>
|
||||
|
||||
setup_byname();
|
||||
|
||||
if (name.ids.size() == 3) {
|
||||
// This is a Site PIP.
|
||||
IdString site_name = name.ids[0];
|
||||
IdString belname = name.ids[1];
|
||||
IdString pinname = name.ids[2];
|
||||
|
||||
int tile;
|
||||
int site;
|
||||
std::tie(tile, site) = site_by_name.at(site_name);
|
||||
auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
|
||||
|
||||
std::array<IdString, 2> ids{name.ids[0], belname};
|
||||
BelId bel = getBelByName(IdStringList(ids));
|
||||
NPNR_ASSERT(bel != BelId());
|
||||
|
||||
int pin_index = get_bel_pin_index(bel, pinname);
|
||||
NPNR_ASSERT(pin_index >= 0);
|
||||
|
||||
for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
|
||||
if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == bel.index &&
|
||||
tile_info.pip_data[i].extra_data == pin_index) {
|
||||
|
||||
PipId ret;
|
||||
ret.tile = tile;
|
||||
ret.index = i;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
auto iter = site_by_name.find(name.ids[0]);
|
||||
if (iter != site_by_name.end()) {
|
||||
// This is either a site pin or a psuedo site pip.
|
||||
// psuedo site pips are <site>/<src site wire>.<dst site wire>
|
||||
// site pins are <site>/<bel>
|
||||
int tile;
|
||||
int site;
|
||||
std::tie(tile, site) = iter->second;
|
||||
auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
|
||||
|
||||
std::string pip_second = name.ids[1].str(this);
|
||||
auto split = pip_second.find('.');
|
||||
if (split == std::string::npos) {
|
||||
// This is a site pin!
|
||||
BelId bel = getBelByName(name);
|
||||
NPNR_ASSERT(bel != BelId());
|
||||
|
||||
for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
|
||||
if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == bel.index) {
|
||||
|
||||
PipId ret;
|
||||
ret.tile = tile;
|
||||
ret.index = i;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// This is a psuedo site pip!
|
||||
IdString src_site_wire = id(pip_second.substr(0, split));
|
||||
IdString dst_site_wire = id(pip_second.substr(split + 1));
|
||||
int32_t src_index = -1;
|
||||
int32_t dst_index = -1;
|
||||
|
||||
for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
|
||||
if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == src_site_wire.index) {
|
||||
src_index = i;
|
||||
if (dst_index != -1) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == dst_site_wire.index) {
|
||||
dst_index = i;
|
||||
if (src_index != -1) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
NPNR_ASSERT(src_index != -1);
|
||||
NPNR_ASSERT(dst_index != -1);
|
||||
|
||||
for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
|
||||
if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].src_index == src_index &&
|
||||
tile_info.pip_data[i].dst_index == dst_index) {
|
||||
|
||||
PipId ret;
|
||||
ret.tile = tile;
|
||||
ret.index = i;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
int tile = tile_by_name.at(name.ids[0]);
|
||||
auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
|
||||
|
||||
std::string pip_second = name.ids[1].str(this);
|
||||
auto spn = split_identifier_name_dot(pip_second);
|
||||
auto src_wire_name = id(spn.first);
|
||||
auto dst_wire_name = id(spn.second);
|
||||
|
||||
int32_t src_index = -1;
|
||||
int32_t dst_index = -1;
|
||||
for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
|
||||
if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == src_wire_name.index) {
|
||||
src_index = i;
|
||||
if (dst_index != -1) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == dst_wire_name.index) {
|
||||
dst_index = i;
|
||||
if (src_index != -1) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
NPNR_ASSERT(src_index != -1);
|
||||
NPNR_ASSERT(dst_index != -1);
|
||||
|
||||
for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
|
||||
if (tile_info.pip_data[i].src_index == src_index && tile_info.pip_data[i].dst_index == dst_index) {
|
||||
|
||||
PipId ret;
|
||||
ret.tile = tile;
|
||||
ret.index = i;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return PipId();
|
||||
}
|
||||
|
||||
IdStringList Arch::getPipName(PipId pip) const
|
||||
{
|
||||
// PIP name structure:
|
||||
// Tile PIP: <tile name>/<source wire name>.<destination wire name>
|
||||
// Psuedo site PIP: <site name>/<input site wire>.<output site wire>
|
||||
// Site PIP: <site name>/<bel name>/<input bel pin name>
|
||||
// Site pin: <site name>/<bel name>
|
||||
NPNR_ASSERT(pip != PipId());
|
||||
auto &tile = chip_info->tiles[pip.tile];
|
||||
auto &tile_type = loc_info(chip_info, pip);
|
||||
auto &pip_info = tile_type.pip_data[pip.index];
|
||||
if (pip_info.site != -1) {
|
||||
// This is either a site pin or a site pip.
|
||||
auto &site = chip_info->sites[tile.sites[pip_info.site]];
|
||||
auto &bel = tile_type.bel_data[pip_info.bel];
|
||||
IdString bel_name(bel.name);
|
||||
if (bel.category == BEL_CATEGORY_LOGIC) {
|
||||
// This is a psuedo pip
|
||||
IdString src_wire_name = IdString(tile_type.wire_data[pip_info.src_index].name);
|
||||
IdString dst_wire_name = IdString(tile_type.wire_data[pip_info.dst_index].name);
|
||||
IdString pip = id(src_wire_name.str(this) + "." + dst_wire_name.str(this));
|
||||
std::array<IdString, 2> ids{id(site.name.get()), pip};
|
||||
return IdStringList(ids);
|
||||
|
||||
} else if (bel.category == BEL_CATEGORY_ROUTING) {
|
||||
// This is a site pip.
|
||||
IdString pin_name(bel.ports[pip_info.extra_data]);
|
||||
std::array<IdString, 3> ids{id(site.name.get()), bel_name, pin_name};
|
||||
return IdStringList(ids);
|
||||
} else {
|
||||
NPNR_ASSERT(bel.category == BEL_CATEGORY_SITE_PORT);
|
||||
// This is a site pin, just the name of the BEL is a unique identifier.
|
||||
std::array<IdString, 2> ids{id(site.name.get()), bel_name};
|
||||
return IdStringList(ids);
|
||||
}
|
||||
} else {
|
||||
// This is a tile pip.
|
||||
IdString src_wire_name = IdString(tile_type.wire_data[pip_info.src_index].name);
|
||||
IdString dst_wire_name = IdString(tile_type.wire_data[pip_info.dst_index].name);
|
||||
IdString pip = id(src_wire_name.str(this) + "." + dst_wire_name.str(this));
|
||||
std::array<IdString, 2> ids{id(std::string(tile.name.get())), pip};
|
||||
return IdStringList(ids);
|
||||
}
|
||||
}
|
||||
|
||||
IdString Arch::getPipType(PipId pip) const { return id("PIP"); }
|
||||
|
||||
std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const { return {}; }
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
BelId Arch::getBelByLocation(Loc loc) const
|
||||
{
|
||||
BelId bi;
|
||||
if (loc.x >= chip_info->width || loc.y >= chip_info->height)
|
||||
return BelId();
|
||||
bi.tile = get_tile_index(loc);
|
||||
auto &li = loc_info(chip_info, bi);
|
||||
|
||||
if (loc.z >= li.bel_data.ssize()) {
|
||||
return BelId();
|
||||
} else {
|
||||
bi.index = loc.z;
|
||||
return bi;
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const { return {}; }
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
|
||||
{
|
||||
int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
|
||||
int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;
|
||||
|
||||
int x0, x1, y0, y1;
|
||||
x0 = src_tile % chip_info->width;
|
||||
x1 = x0;
|
||||
y0 = src_tile / chip_info->width;
|
||||
y1 = y0;
|
||||
auto expand = [&](int x, int y) {
|
||||
x0 = std::min(x0, x);
|
||||
x1 = std::max(x1, x);
|
||||
y0 = std::min(y0, y);
|
||||
y1 = std::max(y1, y);
|
||||
};
|
||||
|
||||
expand(dst_tile % chip_info->width, dst_tile / chip_info->width);
|
||||
|
||||
if (source_locs.count(src))
|
||||
expand(source_locs.at(src).x, source_locs.at(src).y);
|
||||
|
||||
if (sink_locs.count(dst)) {
|
||||
expand(sink_locs.at(dst).x, sink_locs.at(dst).y);
|
||||
}
|
||||
|
||||
return {x0, y0, x1, y1};
|
||||
}
|
||||
|
||||
delay_t Arch::getWireRipupDelayPenalty(WireId wire) const { return getRipupDelayPenalty(); }
|
||||
|
||||
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
bool Arch::pack()
|
||||
{
|
||||
// FIXME: Implement this
|
||||
return false;
|
||||
}
|
||||
|
||||
bool Arch::place()
|
||||
{
|
||||
// FIXME: Implement this
|
||||
return false;
|
||||
}
|
||||
|
||||
bool Arch::route()
|
||||
{
|
||||
// FIXME: Implement this
|
||||
return false;
|
||||
}
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const { return {}; }
|
||||
|
||||
DecalXY Arch::getBelDecal(BelId bel) const
|
||||
{
|
||||
DecalXY decalxy;
|
||||
return decalxy;
|
||||
}
|
||||
|
||||
DecalXY Arch::getWireDecal(WireId wire) const
|
||||
{
|
||||
DecalXY decalxy;
|
||||
return decalxy;
|
||||
}
|
||||
|
||||
DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
|
||||
|
||||
DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
delay_t Arch::estimateDelay(WireId src, WireId dst, bool debug) const
|
||||
{
|
||||
// FIXME: Implement something to push the A* router in the right direction.
|
||||
return 0;
|
||||
}
|
||||
|
||||
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
|
||||
{
|
||||
// FIXME: Implement when adding timing-driven place and route.
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
||||
{
|
||||
// FIXME: Implement when adding timing-driven place and route.
|
||||
return false;
|
||||
}
|
||||
|
||||
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
||||
{
|
||||
// FIXME: Implement when adding timing-driven place and route.
|
||||
return TMG_IGNORE;
|
||||
}
|
||||
|
||||
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
|
||||
{
|
||||
// FIXME: Implement when adding timing-driven place and route.
|
||||
TimingClockingInfo info;
|
||||
return info;
|
||||
}
|
||||
|
||||
#ifdef WITH_HEAP
|
||||
const std::string Arch::defaultPlacer = "heap";
|
||||
#else
|
||||
const std::string Arch::defaultPlacer = "sa";
|
||||
#endif
|
||||
|
||||
const std::vector<std::string> Arch::availablePlacers = {"sa",
|
||||
#ifdef WITH_HEAP
|
||||
"heap"
|
||||
#endif
|
||||
};
|
||||
|
||||
const std::string Arch::defaultRouter = "router2";
|
||||
const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
1277
fpga_interchange/arch.h
Normal file
1277
fpga_interchange/arch.h
Normal file
File diff suppressed because it is too large
Load Diff
77
fpga_interchange/arch_pybindings.cc
Normal file
77
fpga_interchange/arch_pybindings.cc
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2020 David Shah <dave@ds0.me>
|
||||
* Copyright (C) 2021 Symbiflow Authors
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "arch_pybindings.h"
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
void arch_wrap_python(py::module &m)
|
||||
{
|
||||
using namespace PythonConversion;
|
||||
py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("chipdb", &ArchArgs::chipdb);
|
||||
|
||||
py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);
|
||||
|
||||
py::class_<WireId>(m, "WireId").def_readwrite("index", &WireId::index);
|
||||
|
||||
py::class_<PipId>(m, "PipId").def_readwrite("index", &PipId::index);
|
||||
|
||||
auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
|
||||
auto ctx_cls = py::class_<Context, Arch>(m, "Context")
|
||||
.def("checksum", &Context::checksum)
|
||||
.def("pack", &Context::pack)
|
||||
.def("place", &Context::place)
|
||||
.def("route", &Context::route);
|
||||
|
||||
fn_wrapper_2a<Context, decltype(&Context::isValidBelForCell), &Context::isValidBelForCell, pass_through<bool>,
|
||||
addr_and_unwrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "isValidBelForCell");
|
||||
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
|
||||
typedef std::unordered_map<IdString, IdString> AliasMap;
|
||||
typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
|
||||
|
||||
auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin");
|
||||
readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
|
||||
readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
|
||||
|
||||
typedef FilteredBelRange BelRangeForBelBucket;
|
||||
#include "arch_pybindings_shared.h"
|
||||
|
||||
WRAP_RANGE(m, BelBucket, conv_to_str<BelBucketId>);
|
||||
WRAP_RANGE(m, Bel, conv_to_str<BelId>);
|
||||
WRAP_RANGE(m, Wire, conv_to_str<WireId>);
|
||||
WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
|
||||
WRAP_RANGE(m, UphillPip, conv_to_str<PipId>);
|
||||
WRAP_RANGE(m, DownhillPip, conv_to_str<PipId>);
|
||||
WRAP_RANGE(m, BelPin, wrap_context<BelPin>);
|
||||
|
||||
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
|
||||
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
|
||||
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif // NO_PYTHON
|
||||
110
fpga_interchange/arch_pybindings.h
Normal file
110
fpga_interchange/arch_pybindings.h
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2020 David Shah <dave@ds0.me>
|
||||
* Copyright (C) 2021 Symbiflow Authors
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef ARCH_PYBINDINGS_H
|
||||
#define ARCH_PYBINDINGS_H
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
namespace PythonConversion {
|
||||
|
||||
template <> struct string_converter<BelId>
|
||||
{
|
||||
BelId from_str(Context *ctx, std::string name) { return ctx->getBelByName(IdStringList::parse(ctx, name)); }
|
||||
|
||||
std::string to_str(Context *ctx, BelId id)
|
||||
{
|
||||
if (id == BelId())
|
||||
throw bad_wrap();
|
||||
return ctx->getBelName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<WireId>
|
||||
{
|
||||
WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(IdStringList::parse(ctx, name)); }
|
||||
|
||||
std::string to_str(Context *ctx, WireId id)
|
||||
{
|
||||
if (id == WireId())
|
||||
throw bad_wrap();
|
||||
return ctx->getWireName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<const WireId>
|
||||
{
|
||||
WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(IdStringList::parse(ctx, name)); }
|
||||
|
||||
std::string to_str(Context *ctx, WireId id)
|
||||
{
|
||||
if (id == WireId())
|
||||
throw bad_wrap();
|
||||
return ctx->getWireName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<PipId>
|
||||
{
|
||||
PipId from_str(Context *ctx, std::string name) { return ctx->getPipByName(IdStringList::parse(ctx, name)); }
|
||||
|
||||
std::string to_str(Context *ctx, PipId id)
|
||||
{
|
||||
if (id == PipId())
|
||||
throw bad_wrap();
|
||||
return ctx->getPipName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<BelBucketId>
|
||||
{
|
||||
BelBucketId from_str(Context *ctx, std::string name) { return ctx->getBelBucketByName(ctx->id(name)); }
|
||||
|
||||
std::string to_str(Context *ctx, BelBucketId id)
|
||||
{
|
||||
if (id == BelBucketId())
|
||||
throw bad_wrap();
|
||||
return ctx->getBelBucketName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<BelPin>
|
||||
{
|
||||
BelPin from_str(Context *ctx, std::string name)
|
||||
{
|
||||
NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
|
||||
}
|
||||
|
||||
std::string to_str(Context *ctx, BelPin pin)
|
||||
{
|
||||
if (pin.bel == BelId())
|
||||
throw bad_wrap();
|
||||
return ctx->getBelName(pin.bel).str(ctx) + "/" + pin.pin.str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace PythonConversion
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
#endif
|
||||
#endif
|
||||
192
fpga_interchange/archdefs.h
Normal file
192
fpga_interchange/archdefs.h
Normal file
@ -0,0 +1,192 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||
* Copyright (C) 2021 Symbiflow Authors
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "archdefs.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
typedef int delay_t;
|
||||
|
||||
struct DelayInfo
|
||||
{
|
||||
delay_t delay = 0;
|
||||
|
||||
delay_t minRaiseDelay() const { return delay; }
|
||||
delay_t maxRaiseDelay() const { return delay; }
|
||||
|
||||
delay_t minFallDelay() const { return delay; }
|
||||
delay_t maxFallDelay() const { return delay; }
|
||||
|
||||
delay_t minDelay() const { return delay; }
|
||||
delay_t maxDelay() const { return delay; }
|
||||
|
||||
DelayInfo operator+(const DelayInfo &other) const
|
||||
{
|
||||
DelayInfo ret;
|
||||
ret.delay = this->delay + other.delay;
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
struct BelId
|
||||
{
|
||||
// Tile that contains this BEL.
|
||||
int32_t tile = -1;
|
||||
// Index into tile type BEL array.
|
||||
// BEL indicies are the same for all tiles of the same type.
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const BelId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct WireId
|
||||
{
|
||||
// Tile that contains this wire.
|
||||
int32_t tile = -1;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const WireId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct PipId
|
||||
{
|
||||
int32_t tile = -1;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const PipId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct GroupId
|
||||
{
|
||||
bool operator==(const GroupId &other) const { return true; }
|
||||
bool operator!=(const GroupId &other) const { return false; }
|
||||
};
|
||||
|
||||
struct DecalId
|
||||
{
|
||||
bool operator==(const DecalId &other) const { return true; }
|
||||
bool operator!=(const DecalId &other) const { return false; }
|
||||
};
|
||||
|
||||
struct BelBucketId
|
||||
{
|
||||
IdString name;
|
||||
|
||||
bool operator==(const BelBucketId &other) const { return (name == other.name); }
|
||||
bool operator!=(const BelBucketId &other) const { return (name != other.name); }
|
||||
bool operator<(const BelBucketId &other) const { return name < other.name; }
|
||||
};
|
||||
|
||||
struct ArchNetInfo
|
||||
{
|
||||
};
|
||||
|
||||
struct NetInfo;
|
||||
|
||||
struct ArchCellInfo
|
||||
{
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
namespace std {
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<int>()(bel.tile));
|
||||
boost::hash_combine(seed, hash<int>()(bel.index));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<int>()(wire.tile));
|
||||
boost::hash_combine(seed, hash<int>()(wire.index));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<int>()(pip.tile));
|
||||
boost::hash_combine(seed, hash<int>()(pip.index));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX GroupId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX GroupId &group) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DecalId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DecalId &decal) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelBucketId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelBucketId &bucket) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(bucket.name));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace std
|
||||
0
fpga_interchange/family.cmake
Normal file
0
fpga_interchange/family.cmake
Normal file
84
fpga_interchange/main.cc
Normal file
84
fpga_interchange/main.cc
Normal file
@ -0,0 +1,84 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||
* Copyright (C) 2021 Symbiflow Authors
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef MAIN_EXECUTABLE
|
||||
|
||||
#include <fstream>
|
||||
#include "command.h"
|
||||
#include "design_utils.h"
|
||||
#include "jsonwrite.h"
|
||||
#include "log.h"
|
||||
#include "timing.h"
|
||||
|
||||
USING_NEXTPNR_NAMESPACE
|
||||
|
||||
class FpgaInterchangeCommandHandler : public CommandHandler
|
||||
{
|
||||
public:
|
||||
FpgaInterchangeCommandHandler(int argc, char **argv);
|
||||
virtual ~FpgaInterchangeCommandHandler(){};
|
||||
std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override;
|
||||
void setupArchContext(Context *ctx) override{};
|
||||
void customBitstream(Context *ctx) override;
|
||||
void customAfterLoad(Context *ctx) override;
|
||||
|
||||
protected:
|
||||
po::options_description getArchOptions() override;
|
||||
};
|
||||
|
||||
FpgaInterchangeCommandHandler::FpgaInterchangeCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
|
||||
|
||||
po::options_description FpgaInterchangeCommandHandler::getArchOptions()
|
||||
{
|
||||
po::options_description specific("Architecture specific options");
|
||||
specific.add_options()("chipdb", po::value<std::string>(), "name of chip database binary");
|
||||
specific.add_options()("xdc", po::value<std::vector<std::string>>(), "XDC-style constraints file");
|
||||
specific.add_options()("phys", po::value<std::string>(), "FPGA interchange Physical netlist to write");
|
||||
|
||||
return specific;
|
||||
}
|
||||
|
||||
void FpgaInterchangeCommandHandler::customBitstream(Context *ctx)
|
||||
{
|
||||
if (vm.count("phys")) {
|
||||
std::string filename = vm["phys"].as<std::string>();
|
||||
ctx->write_physical_netlist(filename);
|
||||
}
|
||||
}
|
||||
|
||||
std::unique_ptr<Context> FpgaInterchangeCommandHandler::createContext(std::unordered_map<std::string, Property> &values)
|
||||
{
|
||||
ArchArgs chipArgs;
|
||||
if (!vm.count("chipdb")) {
|
||||
log_error("chip database binary must be provided\n");
|
||||
}
|
||||
chipArgs.chipdb = vm["chipdb"].as<std::string>();
|
||||
return std::unique_ptr<Context>(new Context(chipArgs));
|
||||
}
|
||||
|
||||
void FpgaInterchangeCommandHandler::customAfterLoad(Context *ctx) {}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
FpgaInterchangeCommandHandler handler(argc, argv);
|
||||
return handler.exec();
|
||||
}
|
||||
|
||||
#endif
|
||||
0
gui/fpga_interchange/family.cmake
Normal file
0
gui/fpga_interchange/family.cmake
Normal file
50
gui/fpga_interchange/mainwindow.cc
Normal file
50
gui/fpga_interchange/mainwindow.cc
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
|
||||
* Copyright (C) 2021 Symbiflow Authors
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "mainwindow.h"
|
||||
|
||||
#include <QMessageBox>
|
||||
#include <cstdlib>
|
||||
|
||||
static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
|
||||
: BaseMainWindow(std::move(context), handler, parent)
|
||||
{
|
||||
initMainResource();
|
||||
QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-generic");
|
||||
std::exit(1);
|
||||
}
|
||||
|
||||
MainWindow::~MainWindow() {}
|
||||
|
||||
void MainWindow::newContext(Context *ctx)
|
||||
{
|
||||
std::string title = "nextpnr-generic - " + ctx->getChipName();
|
||||
setWindowTitle(title.c_str());
|
||||
}
|
||||
|
||||
void MainWindow::createMenu() {}
|
||||
|
||||
void MainWindow::new_proj() {}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
46
gui/fpga_interchange/mainwindow.h
Normal file
46
gui/fpga_interchange/mainwindow.h
Normal file
@ -0,0 +1,46 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
|
||||
* Copyright (C) 2021 Symbiflow Authors
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef MAINWINDOW_H
|
||||
#define MAINWINDOW_H
|
||||
|
||||
#include "../basewindow.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
class MainWindow : public BaseMainWindow
|
||||
{
|
||||
Q_OBJECT
|
||||
|
||||
public:
|
||||
explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
|
||||
virtual ~MainWindow();
|
||||
|
||||
public:
|
||||
void createMenu();
|
||||
|
||||
protected Q_SLOTS:
|
||||
void new_proj() override;
|
||||
void newContext(Context *ctx);
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif // MAINWINDOW_H
|
||||
2
gui/fpga_interchange/nextpnr.qrc
Normal file
2
gui/fpga_interchange/nextpnr.qrc
Normal file
@ -0,0 +1,2 @@
|
||||
<RCC>
|
||||
</RCC>
|
||||
Loading…
Reference in New Issue
Block a user