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Fixed port timing classes of DCC ports in the Nexus architecture

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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2022-08-30 17:30:13 +02:00
parent 0f4166fedb
commit 8b6be09809
1 changed files with 11 additions and 4 deletions
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15
nexus/arch.cc
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@ -492,6 +492,15 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
}
int index = get_cell_timing_idx(id_DCS, id_DCS);
return lookup_cell_delay(index, fromPort, toPort, delay);
} else if (cell->type == id_DCC) {
if (fromPort == id_CLKI && toPort == id_CLKO) {
// TODO: Use actual DCC delays
delay.rise.min_delay = 1000;
delay.rise.max_delay = 1000;
delay.fall.min_delay = 1000;
delay.fall.max_delay = 1000;
return true;
}
}
return false;
}
@ -560,11 +569,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
return type;
} else if (cell->type == id_DCC) {
if (port == id_CLKI)
return TMG_CLOCK_INPUT;
else if (port == id_CLKO)
return TMG_GEN_CLOCK;
else if (port == id_CE)
return TMG_COMB_INPUT;
else if (port == id_CLKO)
return TMG_COMB_OUTPUT;
} else if (cell->type == id_DCS) {
// FIXME: Making inputs TMG_CLOCK_INPUT and the output TMG_CLOCK_GEN
// yielded in error in the timing analyzer. For now keep those as